ea033cecf9
Spike, the RISC-V ISA Simulator, implements a functional model of one or more RISC-V harts. The host package provides an alternative solution to qemu. https://github.com/riscv-software-src/riscv-isa-sim Signed-off-by: Julien Olivain <ju.o@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
14 lines
424 B
Plaintext
14 lines
424 B
Plaintext
config BR2_PACKAGE_HOST_RISCV_ISA_SIM
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bool "host riscv-isa-sim"
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depends on BR2_HOST_GCC_AT_LEAST_4_9 # C++1
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help
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Spike, the RISC-V ISA Simulator, implements a functional
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model of one or more RISC-V harts.
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The host package provides an alternative solution to qemu.
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https://github.com/riscv-software-src/riscv-isa-sim
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comment "host riscv-isa-sim needs host gcc >= 4.9"
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depends on !BR2_HOST_GCC_AT_LEAST_4_9
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