ea033cecf9
Spike, the RISC-V ISA Simulator, implements a functional model of one or more RISC-V harts. The host package provides an alternative solution to qemu. https://github.com/riscv-software-src/riscv-isa-sim Signed-off-by: Julien Olivain <ju.o@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> |
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| .. | ||
| 0001-riscv-disable-precompiled-headers.patch | ||
| Config.in.host | ||
| riscv-isa-sim.hash | ||
| riscv-isa-sim.mk | ||