163 lines
5.3 KiB
Plaintext
163 lines
5.3 KiB
Plaintext
diff -Naur linux-2.4.31.org/drivers/net/au1000_eth.c linux-2.4.31/drivers/net/au1000_eth.c
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--- linux-2.4.31.org/drivers/net/au1000_eth.c 2005-01-19 09:09:56.000000000 -0500
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+++ linux-2.4.31/drivers/net/au1000_eth.c 2005-08-22 12:24:31.000000000 -0400
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@@ -595,6 +595,97 @@
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return 0;
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}
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+int ns_83847_reset(struct net_device *dev, int phy_addr)
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+ {
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+ s16 mii_control, timeout;
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+
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+ // printk("ns_reset\n");
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+ mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
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+ mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
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+ mdelay(1);
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+ for (timeout = 100; timeout > 0; --timeout) {
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+ mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
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+ if ((mii_control & MII_CNTL_RESET) == 0)
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+ break;
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+ mdelay(1);
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+ }
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+ if (mii_control & MII_CNTL_RESET) {
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+ printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
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+ return -1;
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+ }
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+ return 0;
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+ }
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+
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+int ns_83847_init(struct net_device *dev, int phy_addr)
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+ {
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+ s16 data;
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+ // printk("ns_init\n");
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+
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+ /* Stop auto-negotiation */
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+ // data = mdio_read(dev, phy_addr, MII_CONTROL);
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+ // mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
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+ // mdio_write(dev, phy_addr, 0, 0x0000);
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+ mdio_write(dev, phy_addr, MII_CONTROL, MII_CNTL_F100 /* | MII_CNTL_FDX */);
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+
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+ /* Set advertisement to 10/100 and Half/Full duplex (full capabilities) */
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+ data = mdio_read(dev, phy_addr, MII_ANADV);
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+ /* obs PAUSE bit */
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+ data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T; /* MII_NWAY_T4 not sopported */ ;
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+ mdio_write(dev, phy_addr, MII_ANADV, data);
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+
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+ /* Bypass led stretching? */
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+ data = mdio_read(dev, phy_addr, MII_NS_PHYCTRL);
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+ data |= MII_NS_PHYCTRL_BP_STRETCH;
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+ mdio_write(dev, phy_addr, MII_NS_PHYCTRL, data);
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+
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+ /* Restart auto-negotiation */
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+ data = mdio_read(dev, phy_addr, MII_CONTROL);
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+ data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
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+ mdio_write(dev, phy_addr, MII_CONTROL, data);
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+
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+ return 0;
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+ }
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+
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+int ns_83847_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
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+ {
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+ u16 mii_data;
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+ struct au1000_private *aup;
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+
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+ if (!dev) {
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+ printk(KERN_ERR "ns_83847_status error: NULL dev\n");
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+ return -1;
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+ }
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+ aup = (struct au1000_private *) dev->priv;
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+
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+ mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
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+ // printk("ns_status: %04x\n", mii_data);
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+ if (mii_data & MII_STAT_LINK) {
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+ *link = 1;
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+ mii_data = mdio_read(dev, aup->phy_addr, MII_NS_PHYSTS);
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+ if (mii_data & MII_NS_PHYSTS_SPEED_10) {
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+ *speed = IF_PORT_10BASET;
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+ dev->if_port = IF_PORT_10BASET;
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+ }
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+ else {
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+ if (mii_data & MII_NS_PHYSTS_DUPLEX_FULL) {
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+ *speed = IF_PORT_100BASEFX;
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+ dev->if_port = IF_PORT_100BASEFX;
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+ }
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+ else {
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+ *speed = IF_PORT_100BASETX;
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+ dev->if_port = IF_PORT_100BASETX;
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+ }
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+ }
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+
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+ }
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+ else {
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+ *link = 0;
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+ *speed = 0;
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+ dev->if_port = IF_PORT_UNKNOWN;
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+ }
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+ return 0;
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+ }
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+
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#ifdef CONFIG_MIPS_BOSPORUS
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int stub_init(struct net_device *dev, int phy_addr)
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{
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@@ -620,6 +711,12 @@
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}
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#endif
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+struct phy_ops ns_83847_ops = {
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+ ns_83847_init,
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+ ns_83847_reset,
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+ ns_83847_status,
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+};
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+
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struct phy_ops bcm_5201_ops = {
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bcm_5201_init,
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bcm_5201_reset,
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@@ -679,6 +776,7 @@
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{"LSI 80227 10/100 BaseT PHY",0x0016,0xf840, &lsi_80227_ops,0},
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{"Intel LXT971A Dual Speed PHY",0x0013,0x78e2, &lxt971a_ops,0},
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{"Kendin KS8995M 10/100 BaseT PHY",0x0022,0x1450, &ks8995m_ops,0},
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+ {"Natsemi DP83847 PHY", 0x2000, 0x5c30, &ns_83847_ops },
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#ifdef CONFIG_MIPS_BOSPORUS
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{"Stub", 0x1234, 0x5678, &stub_ops },
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#endif
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@@ -872,6 +970,8 @@
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}
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}
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}
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+ printk(KERN_ERR "%s: Au1x No MII transceivers found!\n", dev->name);
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+ return -1;
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found:
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#ifdef CONFIG_MIPS_BOSPORUS
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diff -Naur linux-2.4.31.org/drivers/net/au1000_eth.h linux-2.4.31/drivers/net/au1000_eth.h
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--- linux-2.4.31.org/drivers/net/au1000_eth.h 2004-02-18 08:36:31.000000000 -0500
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+++ linux-2.4.31/drivers/net/au1000_eth.h 2005-08-22 12:31:37.000000000 -0400
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@@ -86,6 +86,27 @@
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#define MII_STAT_CAN_TX_FDX 0x4000
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#define MII_STAT_CAN_T4 0x8000
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+/* mii registers for NS 83847 */
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+#define MII_NS_PHYSTS 0x10
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+#define MII_NS_FCSCR 0x14
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+#define MII_NS_RECR 0x15
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+#define MII_NS_PCSR 0x16
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+#define MII_NS_PHYCTRL 0x19
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+#define MII_NS_10BTSCR 0x1a
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+#define MII_NS_CDCTRL 0x1b
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+
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+/* MII_NS_PHYSTS bits */
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+#define MII_NS_PHYSTS_LINK (1)
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+#define MII_NS_PHYSTS_SPEED_10 (1<<1)
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+#define MII_NS_PHYSTS_DUPLEX_FULL (1<<2)
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+
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+/* MII_NS_PHYCTRL bits */
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+#define MII_NS_PHYCTRL_BP_STRETCH (1<<8)
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+
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+/* MII_NS_CDCTRL bits */
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+#define MII_NS_CDCTRL_CD_ENABLE (1<<15)
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+#define MII_NS_CDCTRL_RISETIME (1<<11)
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+#define MII_NS_CDCTRL_FALLTIME (1<<9)
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#define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */
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#define MII_ID1_MODEL 0x03F0 /* model number */
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