Bram Vlerick 81aa9e7b8b board/freescale/common/imx: align u-boot-spl to 4 bytes ... When enable DM for SPL binary, the DTB part of SPL may not 4 bytes aligned. If u-boot-spl is not aligned, the offset of the DDR firmware is not 4 byte aligned when u-boot-spl-ddr.bin is created. This causes the ddr firmware to not be loaded correctly at boot. See imx-mkimage commit https://source.codeaurora.org/external/imx/imx-mkimage/commit/?id=bba038d893046b44683182dba540f104dab80fe7 for the imx-mkimage details. Signed-off-by: Bram Vlerick <bram.vlerick@openpixelsystems.org> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>		2022-08-23 23:29:19 +02:00
..
genimage.cfg.template
genimage.cfg.template_imx8
genimage.cfg.template_no_boot_part	board/freescale/common/imx: place rootfs at proper offset when BR2_LINUX_KERNEL_INSTALL_TARGET=y	2021-11-14 15:15:14 +01:00
genimage.cfg.template_no_boot_part_spl	board/freescale/common/imx: place rootfs at proper offset when BR2_LINUX_KERNEL_INSTALL_TARGET=y	2021-11-14 15:15:14 +01:00
genimage.cfg.template_spl
imx8-bootloader-prepare.sh	board/freescale/common/imx: align u-boot-spl to 4 bytes	2022-08-23 23:29:19 +02:00
post-image.sh