81aa9e7b8b
When enable DM for SPL binary, the DTB part of SPL may not 4 bytes aligned. If u-boot-spl is not aligned, the offset of the DDR firmware is not 4 byte aligned when u-boot-spl-ddr.bin is created. This causes the ddr firmware to not be loaded correctly at boot. See imx-mkimage commit https://source.codeaurora.org/external/imx/imx-mkimage/commit/?id=bba038d893046b44683182dba540f104dab80fe7 for the imx-mkimage details. Signed-off-by: Bram Vlerick <bram.vlerick@openpixelsystems.org> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> |
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