Commit Graph

306 Commits

Author SHA1 Message Date
Romain Naour
92357f4cbe arch/Config.in.x86: fix bonnell typo
Commit [1] added several x86 cpu variant and introduced a typo
(bonnel) on bonnell cpu.

Rename BR2_x86_bonnel to BR2_x86_bonnell without legacy
handling since it never worked.

Fixes:
http://autobuild.buildroot.net/results/2418106d30e07cf09834941e610c75dde78816d2/

[1] 653fa001f3

Signed-off-by: Romain Naour <romain.naour@gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
2022-05-15 20:10:35 +02:00
Thomas Petazzoni
8c925613dc arch/Config.in.arm: re-organize MMU selection
So far, all ARM cores were selecting BR2_ARCH_HAS_MMU_OPTIONAL, except
no-MMU cores which were selecting nothing.

In practice, MMU-capable ARM cores are always used with their MMU
enabled, so it doesn't make sense to support the use case of not using
the MMU on such cores.

Consequently, to simplify things, we group the MMU handling in the
BR2_ARM_CPU_ARM* options: BR2_ARM_CPU_ARMV4, BR2_ARM_CPU_ARMV5,
BR2_ARM_CPU_ARMV6, BR2_ARM_CPU_ARMV7A, BR2_ARM_CPU_ARMV8A all select
BR2_ARCH_HAS_MMU_MANDATORY, while BR2_ARM_CPU_ARMV7M continues to
select nothing, indicating that there is no MMU available at all.

Fixes:

 http://autobuild.buildroot.net/results/33277d4687ca9a04dbfb02c50e5755ff9e55b0b4/ (FLAT
 selected on AArch64)

 http://autobuild.buildroot.net/results/5e34d11393e14fc36fd6e72b69679bc4fd1e3798/ (FLAT
 selected on AArch64 big-endian)

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-04-24 10:49:58 +02:00
Thomas Petazzoni
42a3300ae5 arch/Config.in: remove BR2_ARCH_HAS_MMU_MANDATORY from BR2_aarch64*
Selecting BR2_ARCH_HAS_MMU_MANDATORY from BR2_aarch64 and
BR2_aarch64_be doesn't make much sense, because the actual ARM cores
described in arch/Config.in.arm then all select
BR2_ARCH_HAS_MMU_OPTIONAL. So we end up with both
BR2_ARCH_HAS_MMU_OPTIONAL and BR2_ARCH_HAS_MMU_MANDATORY, which
doesn't make any sense.

To prevent this, we remove the selection of BR2_ARCH_HAS_MMU_MANDATORY
from BR2_aarch64 and BR2_aarch64_be, and let arch/Config.in.arm do its
job. What arch/Config.in.arm does is currently incorrect, but it will
be fixed in a separate commit.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-04-24 10:46:22 +02:00
Thomas Petazzoni
ec190481a7 arch/Config.in.sh: move BR2_ARCH_HAS_MMU_MANDATORY one level up
Now that all SuperH cores have an MMU, and must use it, move back the
select BR2_ARCH_HAS_MMU_MANDATORY one level up.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-04-24 10:45:17 +02:00
Thomas Petazzoni
04ea3d38dd arch: drop support for SH2A
Until commit "arch/Config.in.sh: fixup MMU selection" in this series,
SH2A could either be used with BR2_USE_MMU disabled or BR2_USE_MMU
enabled.

The later made absolutely no sense, since SH2A does not have a MMU:
MMU support was introduced starting from SH3 according to
https://en.wikipedia.org/wiki/SuperH#SH-3

Also, since commit 22d5501e03 ("arch:
tidy up binary formats config"), which was merged in Buildroot
2015.05, the architecture tuple used when BR2_sh2a=y and BR2_USE_MMU
disabled is sh2a-buildroot-uclinux-uclibc, and this was already
unsupported back in the days of Buildroot 2015.08 and binutils 2.24,
causing the build to fail with:

*** BFD does not support target sh2a-buildroot-uclinux-uclibc.

just like it fails to build today with recent version of binutils.

So, this has been broken since 2015.08, and nobody complained. SH2A is
seldom used, so it's time to kill it.

It is worth mentioning that there had been an attempt at resurrecting
SH2 support around 2015 (see https://lwn.net/Articles/647636/) as part
of the J2 core. This effort led to the addition of FDPIC support for
SH2A in the musl C library (and therefore proper ELF binaries, with
shared libraries), but that was never supported in Buildroot. Now that
the J2 project is essentially dead, there is no reason to bother with
this.

Fixes:

  http://autobuild.buildroot.net/results/63d01d33ae30f86b63b9f42a9fea116f2f3e9005/

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-04-24 10:38:52 +02:00
Thomas Petazzoni
aa8a2dacf2 arch/Config.in.sh: fixup MMU selection
BR2_sh selects BR2_ARCH_HAS_MMU_OPTIONAL, which means that it's up to
the user to decide whether he wants to use MMU or not on SuperH
platforms.

However:

 - On SH2A, there is no MMU at all, so being to select "Use MMU"
   doesn't make any sense.

 - On SH4, there is no support for *not* using the MMU, so disabling
   "Use MMU" will cause the build to fail.

In order to fix this, we move the MMU selection to arch/Config.in.sh:

 - BR2_sh2a selects nothing, so that it's always noMMU

 - BR2_sh4* select BR2_ARCH_HAS_MMU_MANDATORY so that the MMU is
   always used.

Fixes:

 http://autobuild.buildroot.net/results/f4d52cabee61ee0f234b03c1ec1bd02e85e7bb20/ (FLAT
 selected with sh4aeb)

 http://autobuild.buildroot.net/results/d1b1dfe449f82944bd48215da3cdffd05797e2e9/ (FLAT
 selected with sh4a)

 http://autobuild.buildroot.net/results/45bc90fd2dde7bb201d7f999db1a8024cf889a06/ (FLAT
 selected with sh4)

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-04-24 10:28:53 +02:00
Joel Stanley
2448ad2687 arch/Config.in.powerpc: Add BR2_POWERPC_CPU_HAS_VSX
Introduced to allow VSX to be selectively enabled for packages that
support it. Initially used by libnss.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
2022-04-14 21:37:23 +02:00
Thomas De Schampheleire
dd8a410eaf core: introduce NORMALIZED_ARCH as non-kernel replacement for KERNEL_ARCH
The variable 'KERNEL_ARCH' is actually a normalized version of
'ARCH'/'BR2_ARCH'. For example, 'arcle' and 'arceb' both become 'arc', just
as all powerpc variants become 'powerpc'.

It is presumably called 'KERNEL_ARCH' because the Linux kernel is typically
the first place where support for a new architecture is added, and thus is
the entity that defines the normalized name.

However, the term 'KERNEL_ARCH' can also be interpreted as 'the architecture
used by the kernel', which need not be exactly the same as 'the normalized
name for a certain arch'. In particular, for cases where a 64-bit
architecture is running a 64-bit kernel but 32-bit userspace. Examples
include:
    * aarch64 architecture, with aarch64 kernel and 32-bit (ARM) userspace
    * x86_64 architecture, with x86_64 kernel and 32-bit (i386) userspace

In such cases, the 'architecture used by the kernel' needs to refer to the
64-bit name (aarch64, x86_64), whereas all userspace applications need to
refer the, potentially normalized, 32-bit name.

This means that there need to be two different variables:

KERNEL_ARCH:     the architecture used by the kernel
NORMALIZED_ARCH: the normalized name for the current userspace architecture

At this moment, both will actually have the same content. But a subsequent
patch will add basic support for situations described above, in which
KERNEL_ARCH may become overwritten to the 64-bit architecture, while
NORMALIZED_ARCH needs to remain the same (32-bit) case.

This commit replaces use of KERNEL_ARCH where actually the userspace arch is
needed.  Places that use KERNEL_ARCH in combination with building of kernel
modules are not touched.
There may be cases where a package builds both a kernel module as userspace,
in which case it may need to know about both KERNEL_ARCH and
NORMALIZED_ARCH, for the case where they differ. But this is to be fixed on
a per-need basis.

Signed-off-by: Thomas De Schampheleire <thomas.de_schampheleire@nokia.com>
Reviewed-by: Romain Naour <romain.naour@gmail.com>
[Arnout: Also rename BR2_KERNEL_ARCH to BR2_NORMALIZED_ARCH]
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
2022-02-08 21:20:23 +01:00
Thomas De Schampheleire
cf198e2299 arch: move definition of KERNEL_ARCH to Config.in.<arch> files
Similar to other arch-specific strings, the 'KERNEL_ARCH' variable can be
determined from Config.in.<arch> files.

Besides aligning with similar strings, this also means simplification: the
big 'sed' covers several architectures not even supported by Buildroot.

Signed-off-by: Thomas De Schampheleire <thomas.de_schampheleire@nokia.com>
Reviewed-by: Romain Naour <romain.naour@gmail.com>
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
2022-02-08 20:55:36 +01:00
Thomas Petazzoni
206ce35161 arch/Config.in.x86: indicate how the CPU variants are ordered
They are loosely ordered according to the ordering of the gcc
documentation. It is not entirely correct as the generic x86-64,
x86-64-v2, x86-64-v3 and x86-64-v4 are listed before i386 in the gcc
documentation, but this nevertheless gives a good explanation for the
overall ordering of the list.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-01-25 08:41:33 +01:00
Thomas Petazzoni
e7b9413056 arch/Config.in.x86: add sapphirerapids, alderlake, rocketlake
These were added in gcc 11.x.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-01-25 08:41:30 +01:00
Thomas Petazzoni
0b84dcf968 arch/Config.in.x86: add cooperlake CPU variant
It was added in gcc 10.x.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-01-25 08:41:28 +01:00
Thomas Petazzoni
ffcefb3a75 arch/Config.in.x86: add goldmont, goldmont-plus, tremont, cascadelake, tigerlake CPU variants
These were added in gcc 9.x. The goldmont, goldmont-plus and tremont
are for the low-power CPUs. While cascadelake and tigerlake are for
the high-end ones.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-01-25 08:41:26 +01:00
Thomas Petazzoni
86a70de48e arch/Config.in.x86: add cannonlake, icelake-client, icelake-server CPU variants
These were added in gcc 8.x.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-01-25 08:41:24 +01:00
Thomas Petazzoni
4fa073c65f arch/Config.in.x86: x86-64-v4 implies AVX512
Now that we have BR2_X86_CPU_HAS_AVX512, we can use it to fix the
x86-64-v4 definition, which implies AVX512 support according to
https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-01-25 08:41:17 +01:00
Thomas Petazzoni
4c0088718e arch/Config.in.x86: add skylake CPU variants
Both skylake and skylake-avx512 were added in gcc 6.x. According to
https://en.wikipedia.org/wiki/Skylake_(microarchitecture) the early
Skylake processors indeed did not have AVX512 support, while the later
ones did, hence the separate gcc options.

Due to this being the first CPU we support with AVX512, this commit
adds BR2_X86_CPU_HAS_AVX512.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-01-25 08:41:14 +01:00
Thomas Petazzoni
3702977799 arch/Config.in.x86: add broadwell Intel CPU variant
It was added in gcc 4.9.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-01-25 08:41:12 +01:00
Thomas Petazzoni
1a21705e73 arch/Config.in.x86: westmere and silvermont were added in gcc 4.9
These were added in gcc commit
d3c11974032e21121a051d423a1d71097edf752f ("Use proper Intel processor
names for -march=/-mtune=") which was merged in gcc 4.9.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-01-25 08:41:10 +01:00
Thomas Petazzoni
653fa001f3 arch/Config.in.x86: add "newer" names for several Intel x86 CPU variants
In gcc commit d3c11974032e21121a051d423a1d71097edf752f ("Use proper
Intel processor names for -march=/-mtune="), which was merged in gcc
4.9, the following replacements were made:

 * corei7     -> nehalem
 * corei7-avx -> sandybridge
 * core-avx-i -> ivybridge
 * core-avx2  -> haswell
 * atom       -> bonnel
 * slm        -> silvermont

So this commit marks the Buildroot options BR2_x86_corei7,
BR2_x86_corei7_avx, BR2_x86_core_avx2 and BR2_x86_atom as deprecated,
and adds the four corresponding options with the newer names.

Note that the older options are still kept because the new option
names are only supported starting gcc 4.9, and we theoretically still
supports targets gcc as old as gcc 4.3.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-01-25 08:41:08 +01:00
Thomas Petazzoni
73d135a695 arch/Config.in.x86: drastically simplify the BR2_ARCH definition
The BR2_ARCH definition is like this:

 * i486 for the i486 platform
 * i586 for a small number of platforms
 * i686 for all other x86 platforms when used in 32-bit, but we
   enumerate their entire list
 * x86_64 for all x86 64-bit platforms

The list for i686 is long and needs to be extended everytime a new
platform is added, with no added value.

So this commit simplifies that by replacing this long list with just:

   default "i686"	  if BR2_i386

This works because Kconfig guarantees us that if an i386 platform
matches an earlier case (i486 or one of the i586 platforms), the i486
and i586 earlier in the list will match.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-01-25 08:41:06 +01:00
Thomas Petazzoni
eeace1cc13 arch/Config.in.x86: add support for x86-64-v2, x86-64-v3, x86-64-v4
In the face of the vast amount of x86-64 CPU architecture variants,
Linux distributions have worked together to define "micro-architecture
levels" in the x86-64 psABI, called x86-64-v2, x86-64-v3 and
x86-64-v4. They standardize a set of CPU features, and GCC since its
version 11.x has support for these micro-architecture levels as
-march= options.

It makes sense to support them in Buildroot, especially for those who
want to build toolchains that aim at targeting a reasonably broad
family of x86-64 processors.

It only really makes sense to use as 64-bit CPUs, and not as 32-bit
ones, so we guard them behind BR2_x86_64.

More details:

 https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex
 https://developers.redhat.com/blog/2021/01/05/building-red-hat-enterprise-linux-9-for-the-x86-64-v2-microarchitecture-level
 https://www.phoronix.com/scan.php?page=news_item&px=GCC-11-x86-64-Feature-Levels
 https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=59482fa1e7243bd905c7e27c92ae2b89c79fff87

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
[yann.morin.1998@free.fr:
  - they are x86-64-only CPUs
  - add gcc commit URL
]
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-01-09 11:30:26 +01:00
Thomas Petazzoni
d6ce2a1681 arch/Config.in.x86: add option for -march=x86-64
We already have support for a wide range of x86-64 CPUs, but we don't
have any option to build for the most generic possible x86-64 CPU, as
made available by the -march=x86-64 GCC option.

This commit makes this option available in Buildroot.

It only really makes sense to use as a 64-bit CPU, and not as a 32-bit
one, so we guard it behind BR2_x86_64.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
[yann.morin.1998@free.fr: it's an x86-64-only CPU]
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2022-01-09 11:30:26 +01:00
Damien Le Moal
343643fdf1 arch/config: Make RISC-V 64-bits MMU optional
Linux supports No-MMU RISC-V 64-bits since kernel version 5.8. Make
MMU optional to enable building for RISC-V 64-bits boards that do not
have one. MMU use of RISC-V 32-bits builds remains mandatory for now.

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
2021-10-27 14:39:01 +02:00
Romain Naour
547d681b45 package/gcc: remove csky version
Remove gcc csky fork since it doesn't build with the latest compilers
(gcc 8, 10, 11 tested) [1].

Removing the csky gcc fork has become unavoidable since the
Buildroot Docker image used by the gitlab CI will switch soon to
Debian bullseye soon [2].

The csky support for csky807 and csky810 has been upstreamed in
gcc 10 [3] and csky860 will be supported by gcc 12 [4]. There is
no info about the csky610. Although the csky architecture is
supported since gcc 10, the support was not enabled in Buildroot.

[1] http://lists.busybox.net/pipermail/buildroot/2021-August/621504.html
[2] 71b8322712
[3] https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=cc7232b999b8336cf4e261407ed9289c77bed1f0
[4] https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=db92bd223e3957ee58b5a0c0fffd8b7766f1def3

Signed-off-by: Romain Naour <romain.naour@gmail.com>
Cc: Guo Ren <ren_guo@c-sky.com>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Asked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2021-10-17 18:59:22 +02:00
Romain Naour
69147f0391 arch/Config.in: disable internal toolchain backend for csky
We are going to remove the gcc fork for csky, first disable
the internal toolchain backend.

Signed-off-by: Romain Naour <romain.naour@gmail.com>
Cc: Guo Ren <ren_guo@c-sky.com>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Asked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2021-10-17 18:59:06 +02:00
Romain Naour
b28e598cec arch: add BR2_ARCH_NEEDS_GCC_AT_LEAST_11
This new symbol will be used by architectures introduced with gcc 11.

[1] https://gcc.gnu.org/gcc-11/changes.html

Signed-off-by: Romain Naour <romain.naour@gmail.com>
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
2021-06-20 18:46:51 +02:00
Vineet Gupta
aefe5934a4 ARC: Add support for generic HS48 processor
For the HS48 processor, BR currently builds with -mcpu=hs4x_rel31 which
generates suboptimal code as it inhibits delay slot and back-back ST and so on.

Enable a new variant to build with -mcpu=hs4x for normal codegen.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
[yann.morin.1998@free.fr:
  - simplify dependencies on MMU page size
  - wrap long lines
]
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2021-01-16 09:58:26 +01:00
Michael Walle
f33009bbd3 arch/Config.in.powerpc: Drop PPC601 support
Linux support was removed in 5.10 [1]. Since no in-tree defconfig
depends on it, just remove it.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch/powerpc?id=f0ed73f3fa2cdca65973659689ec9e46d99a5f60

Reported-by: Romain Naour <romain.naour@gmail.com>
Signed-off-by: Michael Walle <michael@walle.cc>
[yann.morin.1998@free.fr: reorder legacy entry]
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2020-12-15 19:30:03 +01:00
Thomas Petazzoni
6d2f97aabd arch/Config.in.s390x: drop redundant depends on BR2_s390x
The whole arch/Config.in.s390x file is only included by arch/Config.in
if BR2_s390x=y, so having "depends on" conditions on each options of
the choice doesn't make much sense.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
[yann.morin.1998@free.fr: drop first, empty line]
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2020-09-30 21:36:07 +02:00
Alexander Egorenkov
29353bbef7 toolchain: add support for the internal IBM s390x and Z toolchain
Signed-off-by: Alexander Egorenkov <egorenar@linux.ibm.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2020-09-24 22:03:54 +02:00
Alexander Egorenkov
b9a31ea354 arch: add the basic IBM s390x and Z arch support
Signed-off-by: Alexander Egorenkov <egorenar@linux.ibm.com>
[yann.morin.1998@free.fr: drop supperfluous depends on s390x in choice]
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2020-09-24 22:02:03 +02:00
Romain Naour
b92b727d6f arch/Config.in: add BR2_ARCH_NEEDS_GCC_AT_LEAST_10
This new symbol will be used by architectures introduced with gcc 10.

Signed-off-by: Romain Naour <romain.naour@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2020-06-24 21:57:43 +02:00
Nicolas Robin
f6cd56b9ce arch/x86: adds BR2_X86_CPU_HAS_3DNOW flag
Signed-off-by: Nicolas Robin <nrosfs@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2020-05-15 21:47:50 +02:00
Alexey Brodkin
3cc2c6d19a arch/arc: explicitly set "max-page-size" for GNU LD
Back in the day we relied on a default value that used to be 8KiB
and it worked perfectly fine for ARC's default 8KiB page as well as
4 KiB ones, but not for 16 KiB, see [1] for more details.

So that we fixed by setting "max-page-size" if 16KiB pages are in use by
commit d024d369b8 ("arch/arc: Accommodate 16 KiB MMU pages").

But as Yann very rightfully mentioned here [2] we should be setting this
thing explicitly for all page sizes because:
 1. Defaults might change unexpectedly
 2. Explicitly set stuff is better understood
 3. We act similarly to all settings but not only addressing some corner cases

[1] https://git.buildroot.org/buildroot/commit/?id=d024d369b82d2d3d9d4d75489c19e9488202bca0
[2] https://patchwork.ozlabs.org/patch/1212544/#2330647

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Yann E. MORIN <yann.morin.1998@free.fr>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2019-12-25 22:09:52 +01:00
Alexey Brodkin
d024d369b8 arch/arc: Accommodate 16 KiB MMU pages
ARC processors are known for its configurability and one of those
configurable things is MMU page size which might be set to any
power of two from 4 KiB to 16 MiB, though in the Linux kernel we
only support 4, 8 and 16 KiB due to practical considerations.

And the most used setting is 8 KiB thus GNU LD assumes maximum
page size is 8 KiB by default and while this works for smaller
pages (it's OK to align segments by larger value it will be still
peoperly aligned) this breaks execution of user-space apps on HW
with larger pages because Elf sections might very well span across
allocated pages and thus make executable broken.

Simplest example:
------------------------------------>8-----------------------------------
$ arc-linux-gcc test.c
$ arc-linux-readelf --segments a.out

Program Headers:
  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
...
  LOAD           0x000000 0x00010000 0x00010000 0x003e8 0x003e8 R E 0x2000 <-- See
  LOAD           0x001f24 0x00013f24 0x00013f24 0x000f0 0x0010c RW  0x2000
------------------------------------>8-----------------------------------

Fortunately we may override default page size settings with "max-page-size"
linker option this way:
------------------------------------>8-----------------------------------
$ arc-linux-gcc test.c -Wl,-z,max-page-size=16384
$ arc-linux-readelf --segments a.out
Elf file type is EXEC (Executable file)
Entry point 0x102c4
There are 8 program headers, starting at offset 52

Program Headers:
  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
...
  LOAD           0x000000 0x00010000 0x00010000 0x003e8 0x003e8 R E 0x4000 <-- See
  LOAD           0x001f24 0x00015f24 0x00015f24 0x000f0 0x0010c RW  0x4000
------------------------------------>8-----------------------------------

Which we implement with that change.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
[yann.morin.1998@free.fr: fix comment: s/8196/8192/]
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2019-12-22 21:56:21 +01:00
Vineet Gupta
4f115b521a arch/Config.in.arc: introduce the ARC optimized hs38 variant
This corresponds to -mcu=hs38 with mpy-option=9 (64-bit multiplier)

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2019-11-12 21:51:13 +01:00
Mark Corbin
aee39cbf27 arch/riscv: set the default float ABI based on ISA extensions
This patch sets the default floating point ABI based on the ISA
extensions that have been selected rather than defaulting to soft
float.

For 64-bit:

ISA 'D' selects  lp64d
ISA 'F' selects  lp64f
Otherwise select lp64

For 32-bit:

ISA 'D' selects  ilp32d
ISA 'F' selects  ilp32f
Otherwise select ilp32

This change was proposed by Palmer Dabbelt at SiFive.

Signed-off-by: Mark Corbin <mark.corbin@embecosm.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2019-09-19 21:43:53 +02:00
Evgeniy Didin
81fed0c7db ARC: Add support for ARC HS48 v3.1 processor
This patch introduces a recently released significant update to ARC HS
family: ARC HS48.

One of the major ARC HS48 features is dual-issue pipeline which requires a
little bit modified instruction scheduling compared to single-issue cores
(HS38), thus new "-mcpu/--with-cpu=hs4x".

Also to address some peculiarities of early designs based on HS48 we
introduced yet another "-mcpu/--with-cpu=hs4x_rel31" which we're going to use
as well on some of our development boards.

Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: arc-buildroot@synopsys.com
[Peter: fixup check-package warnings]
Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
2019-08-03 17:30:52 +02:00
Alexey Brodkin
a0835675ae ARC: Add support for ARC HS38 with Quad MAC & FPU
We used to build everything for pretty much baseline ARC HS capable
of runnig Linux kernel, which was ARC HS38/48 with MMU and caches.

But there's a fully featured ARC HS with additional support for
 - Dual & quad integer multiply and MAC operations
 - Double-precision floating-point unit

It corresponds to the following ARC HS templates in ARChitect: hs38_slc_full.

In fact existing HSDK board uses exactly this configuration in its SoC
and this is recommended configuration for Linux use-cases.

To make life simpler we have corresponding "-mcpu" and "--with-cpu"
options in ARC GCC port so we're going to use it and get binaries
built accordingly optimized.

And while at it added help message so users may better understand
what they are dealing with.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Peter Korsgaard <peter@korsgaard.com>
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
2019-08-01 11:56:39 +02:00
Yann E. MORIN
b8aad93817 arch/csky: restrict ck610 to the C-SKY gcc port
As Guo explained, upstream gcc does not support abi-v1 (only abi-v2), but
ck610 needs abi-v1 [0] [1]

To simplify things, we make the whole C-SKY architecture require gcc-9
or later, and add a single exception in gcc to force the ck610 to use
the C-SKY port.

Note that this does not change the default gcc version to be used for
C-SKY: the C-SKY port is still always the default one; the gcc-9 version
is only proposed as an alternative (except for ck610, of course).

[0] http://lists.busybox.net/pipermail/buildroot/2019-July/254386.html
[1] package/Makefile.in#73

Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
Cc: Guo Ren <guoren@kernel.org>
Cc: Arnout Vandecappelle <arnout@mind.be>
Cc: Romain Naour <romain.naour@gmail.com>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
2019-08-01 10:15:17 +02:00
Yann E. MORIN
c568b4f37f arch/arc: always needs -matomic with atomic extensions
As reported by Alexey in:
    https://patchwork.ozlabs.org/patch/1087480/
    https://patchwork.ozlabs.org/patch/1087471/

when BR2_ARC_ATOMIC_EXT is enabled, -matomic needs to always be passed
to the compiler to allow atomic instructions to be used. So instead of
passing them through the command-line CFLAGS, we enforce them in the
toolchain wrapper directly.

Reported-by: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
Cc: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Arnout Vandecappelle <arnout@mind.be>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2019-07-18 22:54:36 +02:00
Yann E. MORIN
0b630b5bf3 arch/arm: add two new non-cortex-based armv8.2a cores
The Neoverse N1 CPU was supported in GCC earlier through the codename Ares [1].

[1] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=37cf0ddecfd1eb5c6852a44135af5a92e5103931

Build tested:
https://gitlab.com/kubu93/buildroot/pipelines/60318953

Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
[Romain: rename BR2_ares to BR2_neoverse_n1]
Signed-off-by: Romain Naour <romain.naour@gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
[Arnout: 'aka' instead of 'alias']
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
2019-07-13 23:06:23 +02:00
Yann E. MORIN
e65a173e52 arch/arm: add two new cortex-based armv8.2a cores
The cortex-a76 implements the full amrv8.2a extensions, and some
optional extensions from the armv8.3a, armv8.4a, and armv8.5a sets,
but none of their mandatory extensions, which means that it does not
qualify for better than an armv8.2a:
    https://developer.arm.com/products/processors/cortex-a/cortex-a76
    http://infocenter.arm.com/help/topic/com.arm.doc.100798_0301_00_en/giq1479805174793.html
    http://infocenter.arm.com/help/topic/com.arm.doc.100798_0301_00_en/fjv1477559794375.html

Also, gcc fits it in the armv8.2a category, too:
    https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64-cores.def;h=67ce42fb8aacd4c246295f32151a03b1f318ae44;hb=HEAD#l97

Build tested:
https://gitlab.com/kubu93/buildroot/pipelines/60318953

Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Romain Naour <romain.naour@gmail.com>
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
2019-07-13 23:00:47 +02:00
Yann E. MORIN
ae179dd0cc arch/arm: add two new 64-bit-only armv8a cores
Build tested:
https://gitlab.com/kubu93/buildroot/pipelines/60318953

Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Romain Naour <romain.naour@gmail.com>
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
2019-07-13 23:00:33 +02:00
Yann E. MORIN
b22ee8ad88 arch/arm: saphira is in fact an armv8.4a
... and not an armv8.3a like previously supposed:
    https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=886d991373e4dc5a746d0a33de64f1b36e61eed9

So, change the correspoding labels and comments.

Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Signed-off-by: Romain Naour <romain.naour@gmail.com>
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
2019-07-13 22:59:31 +02:00
Yann E. MORIN
c0d1730153 arch/arm: some cores have a different name with gcc-9
In gcc-9, some cores from the ThunderX familly have been renamed to
their marketting names, i.e. OcteonTX. Subsequently, new core names
have been added to gcc, with the old names still being around.

Update the prompts with the new names as alternative to the existing
names. We still keep the kconfig options as-is, so that we do not need
to add legacy handling.

However, since there is no guarantee for how long gcc will retain
compatibility for the older names, we readily switch over to using the
new names when using a gcc 9-or-later, but keep using the older names
with gcc older than 9.

Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Romain Naour <romain.naour@gmail.com>
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
[Arnout: don't rely on ordering, but make condition explicit]
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
2019-07-13 22:57:42 +02:00
Yann E. MORIN
9f52763043 arch/arm: move dependency on 64-bit down to individual cores
It will make it easier to introduce new variants anywhere in the
list, when those variants have different bitness requirements.

Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Romain Naour <romain.naour@gmail.com>
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
2019-07-13 22:51:51 +02:00
Romain Naour
16951722d7 arch: add BR2_ARCH_NEEDS_GCC_AT_LEAST_9
This new symbol will be used by architectures introduced with gcc 9 and
by external toolchains based on gcc 9.

[1] https://gcc.gnu.org/gcc-9/changes.html

Signed-off-by: Romain Naour <romain.naour@gmail.com>
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2019-06-22 21:38:23 +02:00
Yann E. MORIN
faa13ee580 arch/Config.in.nds32: force syntax colouring to kconfig
It is too sad when an editor picks up the wrong syntax...

Like was done in e837837791 for all the other archs, force
syntax to kconfig for nds32 too.

Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
Cc: Nylon Chen <nylon7@andestech.com>
Reviewed-by:Nylon Chen <nylon7@andestech.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2019-06-20 21:27:20 +02:00
Esben Haabendal
97651ce275 arch: Add support for Westmere targets
The westmere line of x86_64 targets lies between nehalem (corei7) and
sandybridge (corei7-avx).  Allowing use of -march=westmere enables use of
AES instruction set on these targets.

Signed-off-by: Esben Haabendal <esben@geanix.com>
Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
2019-06-13 21:09:51 +02:00