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arch/Config.in.riscv: allow extensions for generic

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The generic extension set 'G' is realy a base with the minimal set of
extensions needed to be comfortable (but not required) to run a
linux-bassed system. Similarly, we consider the custom to be about the
custom set of features (not about a custom core implementing such a
set).

As such, we allow that a core with the G set can have futher extensions
without requiring it to be configured as a custom set.

We drop the intermediate symbols with the prompts, and move the prompts
to the previously hidden symbols, and add a prompt for the I set.

This alows one to clearly see what the generic set is about, without
having to delve into the help and hunt the list of selected symbol.

Note however that the G set implies Zicsr and Zifencei, but we have no
prompt for thos two, because in Buildroot, we assume that they are
mandatory and always present, like the I set (which they previously were
part of).

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
[yann.morin.1998@free.fr:
  - drop the intermediate symbols
  - move prompt to previously hidden symbols
  - add symbol for I
  - update defconfigs
  - reword the commit log accordingly
]
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
This commit is contained in:
Jamie Gibbons 2023-08-18 11:42:59 +01:00 committed by Yann E. MORIN
parent eea0c9f0c9
commit cbd91e89e4
14 changed files with 72 additions and 100 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
arch/Config.in.riscv
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@ -1,26 +1,5 @@
# RISC-V CPU ISA extensions. # RISC-V CPU ISA extensions.
config BR2_RISCV_ISA_RVI
bool
config BR2_RISCV_ISA_RVM
bool
config BR2_RISCV_ISA_RVA
bool
config BR2_RISCV_ISA_RVF
bool
config BR2_RISCV_ISA_RVD
bool
config BR2_RISCV_ISA_RVC
bool
config BR2_RISCV_ISA_RVV
bool
choice choice
prompt "Target Architecture Variant" prompt "Target Architecture Variant"
default BR2_riscv_g default BR2_riscv_g
@ -41,38 +20,31 @@ config BR2_riscv_custom
endchoice endchoice
if BR2_riscv_custom
comment "Instruction Set Extensions" comment "Instruction Set Extensions"
config BR2_RISCV_ISA_CUSTOM_RVM config BR2_RISCV_ISA_RVI
bool "Base Integer (I)"
config BR2_RISCV_ISA_RVM
bool "Integer Multiplication and Division (M)" bool "Integer Multiplication and Division (M)"
select BR2_RISCV_ISA_RVM
config BR2_RISCV_ISA_CUSTOM_RVA config BR2_RISCV_ISA_RVA
bool "Atomic Instructions (A)" bool "Atomic Instructions (A)"
select BR2_RISCV_ISA_RVA
config BR2_RISCV_ISA_CUSTOM_RVF config BR2_RISCV_ISA_RVF
bool "Single-precision Floating-point (F)" bool "Single-precision Floating-point (F)"
select BR2_RISCV_ISA_RVF
config BR2_RISCV_ISA_CUSTOM_RVD config BR2_RISCV_ISA_RVD
bool "Double-precision Floating-point (D)" bool "Double-precision Floating-point (D)"
depends on BR2_RISCV_ISA_RVF depends on BR2_RISCV_ISA_RVF
select BR2_RISCV_ISA_RVD
config BR2_RISCV_ISA_CUSTOM_RVC config BR2_RISCV_ISA_RVC
bool "Compressed Instructions (C)" bool "Compressed Instructions (C)"
select BR2_RISCV_ISA_RVC
config BR2_RISCV_ISA_CUSTOM_RVV config BR2_RISCV_ISA_RVV
bool "Vector Instructions (V)" bool "Vector Instructions (V)"
select BR2_RISCV_ISA_RVV
select BR2_ARCH_NEEDS_GCC_AT_LEAST_12 select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
endif
choice choice
prompt "Target Architecture Size" prompt "Target Architecture Size"
default BR2_RISCV_64 default BR2_RISCV_64

8
configs/andes_ae350_45_defconfig
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@ -1,9 +1,9 @@
BR2_riscv=y BR2_riscv=y
BR2_riscv_custom=y BR2_riscv_custom=y
BR2_RISCV_ISA_CUSTOM_RVM=y BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_CUSTOM_RVF=y BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_CUSTOM_RVD=y BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_CUSTOM_RVC=y BR2_RISCV_ISA_RVC=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_0=y BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_0=y
BR2_GLOBAL_PATCH_DIR="board/andes/ae350/patches" BR2_GLOBAL_PATCH_DIR="board/andes/ae350/patches"
BR2_TARGET_GENERIC_GETTY_PORT="ttyS0" BR2_TARGET_GENERIC_GETTY_PORT="ttyS0"

10
configs/beaglev_defconfig
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@ -1,10 +1,10 @@
BR2_riscv=y BR2_riscv=y
BR2_riscv_custom=y BR2_riscv_custom=y
BR2_RISCV_ISA_CUSTOM_RVM=y BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_CUSTOM_RVA=y BR2_RISCV_ISA_RVA=y
BR2_RISCV_ISA_CUSTOM_RVF=y BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_CUSTOM_RVD=y BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_CUSTOM_RVC=y BR2_RISCV_ISA_RVC=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_13=y BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_13=y
BR2_ROOTFS_POST_BUILD_SCRIPT="board/beaglev/post-build.sh" BR2_ROOTFS_POST_BUILD_SCRIPT="board/beaglev/post-build.sh"
BR2_ROOTFS_POST_IMAGE_SCRIPT="support/scripts/genimage.sh" BR2_ROOTFS_POST_IMAGE_SCRIPT="support/scripts/genimage.sh"

10
configs/canaan_kd233_defconfig
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@ -2,11 +2,11 @@
BR2_riscv=y BR2_riscv=y
BR2_RISCV_64=y BR2_RISCV_64=y
BR2_riscv_custom=y BR2_riscv_custom=y
BR2_RISCV_ISA_CUSTOM_RVM=y BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_CUSTOM_RVA=y BR2_RISCV_ISA_RVA=y
BR2_RISCV_ISA_CUSTOM_RVF=y BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_CUSTOM_RVD=y BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_CUSTOM_RVC=y BR2_RISCV_ISA_RVC=y
# BR2_RISCV_USE_MMU is not set # BR2_RISCV_USE_MMU is not set
BR2_RISCV_ABI_LP64D=y BR2_RISCV_ABI_LP64D=y

10
configs/hifive_unleashed_defconfig
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@ -1,11 +1,11 @@
# Architecture # Architecture
BR2_riscv=y BR2_riscv=y
BR2_riscv_custom=y BR2_riscv_custom=y
BR2_RISCV_ISA_CUSTOM_RVM=y BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_CUSTOM_RVA=y BR2_RISCV_ISA_RVA=y
BR2_RISCV_ISA_CUSTOM_RVF=y BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_CUSTOM_RVD=y BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_CUSTOM_RVC=y BR2_RISCV_ISA_RVC=y
BR2_RISCV_64=y BR2_RISCV_64=y
BR2_RISCV_ABI_LP64D=y BR2_RISCV_ABI_LP64D=y

8
configs/microchip_mpfs_icicle_defconfig
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@ -1,9 +1,9 @@
BR2_riscv=y BR2_riscv=y
BR2_riscv_custom=y BR2_riscv_custom=y
BR2_RISCV_ISA_CUSTOM_RVM=y BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_CUSTOM_RVF=y BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_CUSTOM_RVD=y BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_CUSTOM_RVC=y BR2_RISCV_ISA_RVC=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_1=y BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_1=y
BR2_TARGET_GENERIC_HOSTNAME="mpfs_icicle" BR2_TARGET_GENERIC_HOSTNAME="mpfs_icicle"
BR2_ROOTFS_POST_IMAGE_SCRIPT="board/microchip/mpfs_icicle/post-image.sh" BR2_ROOTFS_POST_IMAGE_SCRIPT="board/microchip/mpfs_icicle/post-image.sh"

10
configs/sipeed_maix_bit_defconfig
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@ -2,11 +2,11 @@
BR2_riscv=y BR2_riscv=y
BR2_RISCV_64=y BR2_RISCV_64=y
BR2_riscv_custom=y BR2_riscv_custom=y
BR2_RISCV_ISA_CUSTOM_RVM=y BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_CUSTOM_RVA=y BR2_RISCV_ISA_RVA=y
BR2_RISCV_ISA_CUSTOM_RVF=y BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_CUSTOM_RVD=y BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_CUSTOM_RVC=y BR2_RISCV_ISA_RVC=y
# BR2_RISCV_USE_MMU is not set # BR2_RISCV_USE_MMU is not set
BR2_RISCV_ABI_LP64D=y BR2_RISCV_ABI_LP64D=y

10
configs/sipeed_maix_bit_sdcard_defconfig
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@ -2,11 +2,11 @@
BR2_riscv=y BR2_riscv=y
BR2_RISCV_64=y BR2_RISCV_64=y
BR2_riscv_custom=y BR2_riscv_custom=y
BR2_RISCV_ISA_CUSTOM_RVM=y BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_CUSTOM_RVA=y BR2_RISCV_ISA_RVA=y
BR2_RISCV_ISA_CUSTOM_RVF=y BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_CUSTOM_RVD=y BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_CUSTOM_RVC=y BR2_RISCV_ISA_RVC=y
# BR2_RISCV_USE_MMU is not set # BR2_RISCV_USE_MMU is not set
BR2_RISCV_ABI_LP64D=y BR2_RISCV_ABI_LP64D=y

10
configs/sipeed_maix_dock_defconfig
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@ -2,11 +2,11 @@
BR2_riscv=y BR2_riscv=y
BR2_RISCV_64=y BR2_RISCV_64=y
BR2_riscv_custom=y BR2_riscv_custom=y
BR2_RISCV_ISA_CUSTOM_RVM=y BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_CUSTOM_RVA=y BR2_RISCV_ISA_RVA=y
BR2_RISCV_ISA_CUSTOM_RVF=y BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_CUSTOM_RVD=y BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_CUSTOM_RVC=y BR2_RISCV_ISA_RVC=y
# BR2_RISCV_USE_MMU is not set # BR2_RISCV_USE_MMU is not set
BR2_RISCV_ABI_LP64D=y BR2_RISCV_ABI_LP64D=y

10
configs/sipeed_maix_dock_sdcard_defconfig
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@ -2,11 +2,11 @@
BR2_riscv=y BR2_riscv=y
BR2_RISCV_64=y BR2_RISCV_64=y
BR2_riscv_custom=y BR2_riscv_custom=y
BR2_RISCV_ISA_CUSTOM_RVM=y BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_CUSTOM_RVA=y BR2_RISCV_ISA_RVA=y
BR2_RISCV_ISA_CUSTOM_RVF=y BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_CUSTOM_RVD=y BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_CUSTOM_RVC=y BR2_RISCV_ISA_RVC=y
# BR2_RISCV_USE_MMU is not set # BR2_RISCV_USE_MMU is not set
BR2_RISCV_ABI_LP64D=y BR2_RISCV_ABI_LP64D=y

10
configs/sipeed_maix_go_defconfig
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@ -2,11 +2,11 @@
BR2_riscv=y BR2_riscv=y
BR2_RISCV_64=y BR2_RISCV_64=y
BR2_riscv_custom=y BR2_riscv_custom=y
BR2_RISCV_ISA_CUSTOM_RVM=y BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_CUSTOM_RVA=y BR2_RISCV_ISA_RVA=y
BR2_RISCV_ISA_CUSTOM_RVF=y BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_CUSTOM_RVD=y BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_CUSTOM_RVC=y BR2_RISCV_ISA_RVC=y
# BR2_RISCV_USE_MMU is not set # BR2_RISCV_USE_MMU is not set
BR2_RISCV_ABI_LP64D=y BR2_RISCV_ABI_LP64D=y

10
configs/sipeed_maix_go_sdcard_defconfig
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@ -2,11 +2,11 @@
BR2_riscv=y BR2_riscv=y
BR2_RISCV_64=y BR2_RISCV_64=y
BR2_riscv_custom=y BR2_riscv_custom=y
BR2_RISCV_ISA_CUSTOM_RVM=y BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_CUSTOM_RVA=y BR2_RISCV_ISA_RVA=y
BR2_RISCV_ISA_CUSTOM_RVF=y BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_CUSTOM_RVD=y BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_CUSTOM_RVC=y BR2_RISCV_ISA_RVC=y
# BR2_RISCV_USE_MMU is not set # BR2_RISCV_USE_MMU is not set
BR2_RISCV_ABI_LP64D=y BR2_RISCV_ABI_LP64D=y

10
configs/sipeed_maixduino_defconfig
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@ -2,11 +2,11 @@
BR2_riscv=y BR2_riscv=y
BR2_RISCV_64=y BR2_RISCV_64=y
BR2_riscv_custom=y BR2_riscv_custom=y
BR2_RISCV_ISA_CUSTOM_RVM=y BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_CUSTOM_RVA=y BR2_RISCV_ISA_RVA=y
BR2_RISCV_ISA_CUSTOM_RVF=y BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_CUSTOM_RVD=y BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_CUSTOM_RVC=y BR2_RISCV_ISA_RVC=y
# BR2_RISCV_USE_MMU is not set # BR2_RISCV_USE_MMU is not set
BR2_RISCV_ABI_LP64D=y BR2_RISCV_ABI_LP64D=y

10
configs/sipeed_maixduino_sdcard_defconfig
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@ -2,11 +2,11 @@
BR2_riscv=y BR2_riscv=y
BR2_RISCV_64=y BR2_RISCV_64=y
BR2_riscv_custom=y BR2_riscv_custom=y
BR2_RISCV_ISA_CUSTOM_RVM=y BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_CUSTOM_RVA=y BR2_RISCV_ISA_RVA=y
BR2_RISCV_ISA_CUSTOM_RVF=y BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_CUSTOM_RVD=y BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_CUSTOM_RVC=y BR2_RISCV_ISA_RVC=y
# BR2_RISCV_USE_MMU is not set # BR2_RISCV_USE_MMU is not set
BR2_RISCV_ABI_LP64D=y BR2_RISCV_ABI_LP64D=y