add configs/zynqmp_kria_kv260_defconfig
This patch adds support for Xilinx Kria KV260 starter kit. KV260 features can be found here: https://www.xilinx.com/products/boards-and-kits/kv260.html While the Kria SOM is based on a ZynqMP SoC, there are some key boot config differences from the other ZynqMP evaluation boards. 1. There are no boot switches on Kria SOMs. The boot mode is thus hard configured for QSPI flash. A pre-programmed boot.bin comes with every Starter Kit. U-Boot can then find the Linux kernel and file system on the SD card. Optional instructions for updating the boot.bin in the QSPI flash can be found in the readme.txt file and the link below. https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM 2. Kria SOMs use UART1 for the console instead of UART0. For this reason, Kria Starter Kits will use a separate extlinux.conf file from other ZynqMP evaluation boards. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
This commit is contained in:
Neal Frager
Peter Korsgaard
parent
45a67a2f83
commit
b73f5c32af
4
board/zynqmp/kria/extlinux.conf
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4
board/zynqmp/kria/extlinux.conf
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@ -0,0 +1,4 @@
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label linux
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kernel /Image
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devicetree /system.dtb
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append console=ttyPS1,115200 root=/dev/mmcblk1p2 rw rootwait
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556
board/zynqmp/kria/kv260/pm_cfg_obj.c
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556
board/zynqmp/kria/kv260/pm_cfg_obj.c
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@ -0,0 +1,556 @@
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/******************************************************************************
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* Copyright (c) 2017 - 2021 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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#include "xil_types.h"
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#include "pm_defs.h"
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#define PM_CONFIG_MASTER_SECTION_ID 0x101U
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#define PM_CONFIG_SLAVE_SECTION_ID 0x102U
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#define PM_CONFIG_PREALLOC_SECTION_ID 0x103U
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#define PM_CONFIG_POWER_SECTION_ID 0x104U
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#define PM_CONFIG_RESET_SECTION_ID 0x105U
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#define PM_CONFIG_SHUTDOWN_SECTION_ID 0x106U
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#define PM_CONFIG_SET_CONFIG_SECTION_ID 0x107U
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#define PM_CONFIG_GPO_SECTION_ID 0x108U
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#define PM_SLAVE_FLAG_IS_SHAREABLE 0x1U
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#define PM_MASTER_USING_SLAVE_MASK 0x2U
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#define PM_CONFIG_GPO1_MIO_PIN_34_MAP (1U << 10U)
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#define PM_CONFIG_GPO1_MIO_PIN_35_MAP (1U << 11U)
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#define PM_CONFIG_GPO1_MIO_PIN_36_MAP (1U << 12U)
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#define PM_CONFIG_GPO1_MIO_PIN_37_MAP (1U << 13U)
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#define PM_CONFIG_GPO1_BIT_2_MASK (1U << 2U)
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#define PM_CONFIG_GPO1_BIT_3_MASK (1U << 3U)
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#define PM_CONFIG_GPO1_BIT_4_MASK (1U << 4U)
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#define PM_CONFIG_GPO1_BIT_5_MASK (1U << 5U)
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#define SUSPEND_TIMEOUT 0xFFFFFFFFU
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#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001
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#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100
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#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200
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#if defined (__ICCARM__)
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#pragma language=save
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#pragma language=extended
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#endif
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#if defined (__GNUC__)
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const u32 XPm_ConfigObject[] __attribute__((used, section(".sys_cfg_data"))) =
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#elif defined (__ICCARM__)
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#pragma location = ".sys_cfg_data"
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__root const u32 XPm_ConfigObject[] =
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#endif
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{
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/**********************************************************************/
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/* HEADER */
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2, /* Number of remaining words in the header */
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8, /* Number of sections included in config object */
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1U, /* Type of config object as base */
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/**********************************************************************/
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/* MASTER SECTION */
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PM_CONFIG_MASTER_SECTION_ID, /* Master SectionID */
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3U, /* No. of Masters*/
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NODE_APU, /* Master Node ID */
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* IPI Mask of this master */
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SUSPEND_TIMEOUT, /* Suspend timeout */
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PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Suspend permissions */
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PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Wake permissions */
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NODE_RPU_0, /* Master Node ID */
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PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask of this master */
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SUSPEND_TIMEOUT, /* Suspend timeout */
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Suspend permissions */
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Wake permissions */
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NODE_RPU_1, /* Master Node ID */
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PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask of this master */
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SUSPEND_TIMEOUT, /* Suspend timeout */
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* Suspend permissions */
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* Wake permissions */
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/**********************************************************************/
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/* SLAVE SECTION */
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PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */
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49, /* Number of slaves */
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NODE_OCM_BANK_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_OCM_BANK_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_OCM_BANK_2,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_OCM_BANK_3,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_TCM_0_A,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
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NODE_TCM_0_B,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
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NODE_TCM_1_A,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_TCM_1_B,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_L2,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_GPU_PP_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_GPU_PP_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_USB_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_USB_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_TTC_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_TTC_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_TTC_2,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_TTC_3,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_SATA,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_ETH_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_ETH_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_ETH_2,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_ETH_3,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_UART_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_UART_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_SPI_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_SPI_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_I2C_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_I2C_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_SD_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_SD_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_DP,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_GDMA,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_ADMA,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_NAND,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_QSPI,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_GPIO,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_CAN_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_CAN_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_EXTERN,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_DDR,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_IPI_APU,
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0U,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* IPI Mask */
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NODE_IPI_RPU_0,
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0U,
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PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
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NODE_IPI_RPU_1,
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0U,
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PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_GPU,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_PCIE,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_PCAP,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_RTC,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_VCU,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_PL,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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/**********************************************************************/
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/* PREALLOC SECTION */
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PM_CONFIG_PREALLOC_SECTION_ID, /* Preallaoc SectionID */
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3U, /* No. of Masters*/
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/* Prealloc for psu_cortexa53_0 */
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK,
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11,
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NODE_DDR,
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PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
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NODE_L2,
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PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
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NODE_OCM_BANK_0,
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PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
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NODE_OCM_BANK_1,
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PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
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NODE_OCM_BANK_2,
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PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
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NODE_OCM_BANK_3,
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PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
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NODE_I2C_1,
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PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
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NODE_SD_1,
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PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
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PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_QSPI,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_PL,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_IPI_APU,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
|
||||
/* Prealloc for psu_cortexr5_0 */
|
||||
PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK,
|
||||
3,
|
||||
NODE_TCM_0_A,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_TCM_0_B,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_IPI_RPU_0,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
|
||||
/* Prealloc for psu_cortexr5_1 */
|
||||
PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
3,
|
||||
NODE_TCM_1_A,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_TCM_1_B,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_IPI_RPU_1,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
|
||||
|
||||
/**********************************************************************/
|
||||
/* POWER SECTION */
|
||||
|
||||
PM_CONFIG_POWER_SECTION_ID, /* Power Section ID */
|
||||
4U, /* Number of power nodes */
|
||||
|
||||
NODE_APU, /* Power node ID */
|
||||
PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
|
||||
|
||||
NODE_RPU, /* Power node ID */
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
|
||||
|
||||
NODE_FPD, /* Power node ID */
|
||||
PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
|
||||
|
||||
NODE_PLD, /* Power node ID */
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
|
||||
|
||||
|
||||
/**********************************************************************/
|
||||
/* RESET SECTION */
|
||||
|
||||
PM_CONFIG_RESET_SECTION_ID, /* Reset Section ID */
|
||||
120U, /* Number of resets */
|
||||
|
||||
XILPM_RESET_PCIE_CFG, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_PCIE_BRIDGE, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_PCIE_CTRL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_DP, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SWDT_CRF, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_AFI_FM5, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_AFI_FM4, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_AFI_FM3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_AFI_FM2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_AFI_FM1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_AFI_FM0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GDMA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPU_PP1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPU_PP0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPU, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SATA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU3_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU2_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU1_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU0_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_APU_L2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_DDR, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_APM_FPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SOFT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GEM0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GEM1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GEM2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GEM3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_QSPI, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_UART0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_UART1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SPI0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SPI1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SDIO0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SDIO1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_CAN0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_CAN1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_I2C0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_I2C1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_TTC0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_TTC1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_TTC2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_TTC3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SWDT_CRL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_NAND, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ADMA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPIO, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_IOU_CC, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_TIMESTAMP, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RPU_R50, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RPU_R51, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RPU_AMBA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_OCM, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RPU_PGE, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_USB0_CORERESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_USB1_CORERESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_USB0_HIBERRESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_USB1_HIBERRESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_USB0_APB, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_USB1_APB, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_IPI, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_APM_LPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RTC, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SYSMON, 0,
|
||||
XILPM_RESET_AFI_FM6, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_LPD_SWDT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_FPD, PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK,
|
||||
XILPM_RESET_RPU_DBG1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RPU_DBG0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_DBG_LPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_DBG_FPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_APLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_DPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_VPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_IOPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_4, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_5, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_6, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_7, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_8, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_9, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_10, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_11, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_12, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_13, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_14, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_15, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_16, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_17, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_18, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_19, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_20, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_21, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_22, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_23, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_24, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_25, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_26, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_27, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_28, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_29, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_30, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_31, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RPU_LS, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_PS_ONLY, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_PL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPIO5_EMIO_92, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPIO5_EMIO_93, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPIO5_EMIO_94, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPIO5_EMIO_95, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
|
||||
/**********************************************************************/
|
||||
/* SET CONFIG SECTION */
|
||||
PM_CONFIG_SET_CONFIG_SECTION_ID, /* Set Config Section ID */
|
||||
0U, /* Permissions to load base config object */
|
||||
0U, /* Permissions to load overlay config object */
|
||||
|
||||
/**********************************************************************/
|
||||
/* SHUTDOWN SECTION */
|
||||
|
||||
PM_CONFIG_SHUTDOWN_SECTION_ID, /* Shutdown Section ID */
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* System Shutdown/Restart Permission */
|
||||
|
||||
/**********************************************************************/
|
||||
/* GPO SECTION */
|
||||
PM_CONFIG_GPO_SECTION_ID, /* GPO Section ID */
|
||||
PM_CONFIG_GPO1_BIT_2_MASK |
|
||||
PM_CONFIG_GPO1_MIO_PIN_34_MAP |
|
||||
PM_CONFIG_GPO1_MIO_PIN_35_MAP |
|
||||
0, /* State of GPO pins */
|
||||
};
|
||||
#if defined (__ICCARM__)
|
||||
#pragma language=restore
|
||||
#endif
|
||||
|
||||
1
board/zynqmp/kria/kv260/uboot.fragment
Normal file
1
board/zynqmp/kria/kv260/uboot.fragment
Normal file
@ -0,0 +1 @@
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-smk-k26-revA"
|
||||
8
board/zynqmp/kria/post-build.sh
Executable file
8
board/zynqmp/kria/post-build.sh
Executable file
@ -0,0 +1,8 @@
|
||||
#!/bin/sh
|
||||
|
||||
# genimage will need to find the extlinux.conf
|
||||
# in the binaries directory
|
||||
|
||||
BOARD_DIR="$(dirname $0)"
|
||||
|
||||
install -m 0644 -D $BOARD_DIR/extlinux.conf $BINARIES_DIR/extlinux.conf
|
||||
78
board/zynqmp/kria/readme.txt
Normal file
78
board/zynqmp/kria/readme.txt
Normal file
@ -0,0 +1,78 @@
|
||||
**************************************************
|
||||
Xilinx Kria SOM Starter Kits - ZynqMP SoC
|
||||
**************************************************
|
||||
|
||||
This document describes the Buildroot support for the Kria
|
||||
KV260 starter kit by Xilinx, based on Kria SOM including the
|
||||
Zynq UltraScale+ MPSoC (aka ZynqMP). It has been tested with
|
||||
the KV260 production board.
|
||||
|
||||
Evaluation board features can be found here with the link below.
|
||||
|
||||
KV260:
|
||||
https://www.xilinx.com/products/boards-and-kits/kv260.html
|
||||
|
||||
How to build it
|
||||
===============
|
||||
|
||||
Configure Buildroot:
|
||||
|
||||
$ make zynqmp_kria_kv260_defconfig
|
||||
|
||||
Compile everything and build the rootfs image:
|
||||
|
||||
$ make
|
||||
|
||||
Result of the build
|
||||
-------------------
|
||||
|
||||
After building, you should get a tree like this:
|
||||
|
||||
output/images/
|
||||
+-- atf-uboot.ub
|
||||
+-- bl31.bin
|
||||
+-- boot.bin
|
||||
+-- boot.vfat
|
||||
+-- Image
|
||||
+-- rootfs.ext2
|
||||
+-- rootfs.ext4 -> rootfs.ext2
|
||||
+-- sdcard.img
|
||||
+-- system.dtb -> smk-k26-revA-sck-kv-g-revB.dtb
|
||||
+-- u-boot.itb
|
||||
`-- smk-k26-revA-sck-kv-g-revB.dtb
|
||||
|
||||
How to write the SD card
|
||||
========================
|
||||
|
||||
WARNING! This will destroy all the card content. Use with care!
|
||||
|
||||
The sdcard.img file is a complete bootable image ready to be written
|
||||
on the boot medium. To install it, simply copy the image to an SD
|
||||
card:
|
||||
|
||||
# dd if=output/images/sdcard.img of=/dev/sdX
|
||||
|
||||
Where 'sdX' is the device node of the SD.
|
||||
|
||||
Eject the SD card, insert it in the board, and power it up.
|
||||
|
||||
How to write the boot.bn to QSPI boot flash
|
||||
===========================================
|
||||
|
||||
The Kria SOMs are preconfigured to boot initially from QSPI.
|
||||
This makes these boards different from other ZynqMP boards
|
||||
in that the boot.bin needs to be flashed into the QSPI boot
|
||||
flash such that the U-Boot SPL can then load all of the
|
||||
remaining images from the SD card.
|
||||
|
||||
In addition, the KV260 Starter Kit QSPI comes pre-flashed with
|
||||
a utility designed to make updating the QSPI flash memory
|
||||
easier.
|
||||
|
||||
Instructions for using these utilities to update the boot.bin
|
||||
in QSPI flash can be found on the wiki link below.
|
||||
|
||||
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM#Boot-Firmware-Updates
|
||||
|
||||
It is possible to boot the Buildroot generated SD card image without
|
||||
updating the QSPI boot.bin image, so this is an optional step.
|
||||
37
configs/zynqmp_kria_kv260_defconfig
Normal file
37
configs/zynqmp_kria_kv260_defconfig
Normal file
@ -0,0 +1,37 @@
|
||||
BR2_aarch64=y
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_15=y
|
||||
BR2_ROOTFS_POST_BUILD_SCRIPT="board/zynqmp/kria/post-build.sh"
|
||||
BR2_ROOTFS_POST_IMAGE_SCRIPT="board/zynqmp/post-image.sh"
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xlnx_rebase_v5.15_LTS_2022.1)/xlnx_rebase_v5.15_LTS_2022.1.tar.gz"
|
||||
BR2_LINUX_KERNEL_DEFCONFIG="xilinx_zynqmp"
|
||||
BR2_LINUX_KERNEL_DTS_SUPPORT=y
|
||||
BR2_LINUX_KERNEL_INTREE_DTS_NAME="xilinx/smk-k26-revA-sck-kv-g-revB"
|
||||
BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
|
||||
BR2_TARGET_ROOTFS_EXT2=y
|
||||
BR2_TARGET_ROOTFS_EXT2_4=y
|
||||
# BR2_TARGET_ROOTFS_TAR is not set
|
||||
BR2_TARGET_ARM_TRUSTED_FIRMWARE=y
|
||||
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL=y
|
||||
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,arm-trusted-firmware,xlnx_rebase_v2.6_2022.1)/xlnx_rebase_v2.6_2022.1.tar.gz"
|
||||
BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="zynqmp"
|
||||
BR2_TARGET_ARM_TRUSTED_FIRMWARE_BL31_UBOOT=y
|
||||
BR2_TARGET_UBOOT=y
|
||||
BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
|
||||
BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
|
||||
BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,u-boot-xlnx,xlnx_rebase_v2022.01_2022.1)/xlnx_rebase_v2022.01_2022.1.tar.gz"
|
||||
BR2_TARGET_UBOOT_BOARD_DEFCONFIG="xilinx_zynqmp_virt"
|
||||
BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES="board/zynqmp/kria/kv260/uboot.fragment"
|
||||
BR2_TARGET_UBOOT_NEEDS_DTC=y
|
||||
BR2_TARGET_UBOOT_NEEDS_OPENSSL=y
|
||||
BR2_TARGET_UBOOT_SPL=y
|
||||
BR2_TARGET_UBOOT_SPL_NAME="spl/boot.bin"
|
||||
BR2_TARGET_UBOOT_ZYNQMP=y
|
||||
BR2_TARGET_UBOOT_ZYNQMP_PMUFW="https://github.com/lucaceresoli/zynqmp-pmufw-binaries/raw/v2022.1/bin/pmufw-v2022.1.bin"
|
||||
BR2_TARGET_UBOOT_ZYNQMP_PM_CFG="board/zynqmp/kria/kv260/pm_cfg_obj.c"
|
||||
BR2_TARGET_UBOOT_FORMAT_ITB=y
|
||||
BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y
|
||||
BR2_PACKAGE_HOST_DOSFSTOOLS=y
|
||||
BR2_PACKAGE_HOST_GENIMAGE=y
|
||||
BR2_PACKAGE_HOST_MTOOLS=y
|
||||
Loading…
Reference in New Issue
Block a user