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arch/riscv: enable RISC-V Toolchain with Vector Extension

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This commits adds support for building a RISC-V toolchain with the
vector extension, available since gcc 12.

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
This commit is contained in:
Tianrui Wei 2023-06-09 17:46:42 +00:00 committed by Thomas Petazzoni
parent 7252098696
commit 4d70454754
2 changed files with 12 additions and 0 deletions
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9
arch/Config.in.riscv
View File

@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD
config BR2_RISCV_ISA_RVC
bool
config BR2_RISCV_ISA_RVV
bool
choice
prompt "Target Architecture Variant"
default BR2_riscv_g
@ -62,6 +65,12 @@ config BR2_RISCV_ISA_CUSTOM_RVD
config BR2_RISCV_ISA_CUSTOM_RVC
bool "Compressed Instructions (C)"
select BR2_RISCV_ISA_RVC
config BR2_RISCV_ISA_CUSTOM_RVV
bool "Vector Instructions (V)"
select BR2_RISCV_ISA_RVV
select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
endif
choice

3
arch/arch.mk.riscv
View File

@ -26,6 +26,9 @@ endif
ifeq ($(BR2_RISCV_ISA_RVC),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
endif
ifeq ($(BR2_RISCV_ISA_RVV),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v
endif
# Starting from gcc 12.x, csr and fence instructions have been
# separated from the base I instruction set, and special -march