From 4d70454754142a6334ec4a7e8cc6582bbf2f4b9d Mon Sep 17 00:00:00 2001 From: Tianrui Wei Date: Fri, 9 Jun 2023 17:46:42 +0000 Subject: [PATCH] arch/riscv: enable RISC-V Toolchain with Vector Extension This commits adds support for building a RISC-V toolchain with the vector extension, available since gcc 12. Signed-off-by: Tianrui Wei Signed-off-by: Thomas Petazzoni --- arch/Config.in.riscv | 9 +++++++++ arch/arch.mk.riscv | 3 +++ 2 files changed, 12 insertions(+) diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv index 853e8deb06..3dfbb4165f 100644 --- a/arch/Config.in.riscv +++ b/arch/Config.in.riscv @@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD config BR2_RISCV_ISA_RVC bool +config BR2_RISCV_ISA_RVV + bool + choice prompt "Target Architecture Variant" default BR2_riscv_g @@ -62,6 +65,12 @@ config BR2_RISCV_ISA_CUSTOM_RVD config BR2_RISCV_ISA_CUSTOM_RVC bool "Compressed Instructions (C)" select BR2_RISCV_ISA_RVC + +config BR2_RISCV_ISA_CUSTOM_RVV + bool "Vector Instructions (V)" + select BR2_RISCV_ISA_RVV + select BR2_ARCH_NEEDS_GCC_AT_LEAST_12 + endif choice diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv index 8d2236147c..ee5c434b97 100644 --- a/arch/arch.mk.riscv +++ b/arch/arch.mk.riscv @@ -26,6 +26,9 @@ endif ifeq ($(BR2_RISCV_ISA_RVC),y) GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c endif +ifeq ($(BR2_RISCV_ISA_RVV),y) +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v +endif # Starting from gcc 12.x, csr and fence instructions have been # separated from the base I instruction set, and special -march