Esben Haabendal b2a4e994b5 arch: Add support for Westmere targets ... The westmere line of x86_64 targets lies between nehalem (corei7) and sandybridge (corei7-avx). Allowing use of -march=westmere enables use of AES instruction set on these targets. Signed-off-by: Esben Haabendal <esben@geanix.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com> (cherry picked from commit 97651ce275) Signed-off-by: Peter Korsgaard <peter@korsgaard.com>		2019-06-23 23:09:07 +02:00
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arch.mk	arch: drop BR2_GCC_TARGET_CPU_REVISION option	2018-10-01 14:52:32 +02:00
arch.mk.riscv	arch: add support for RISC-V 32-bit (riscv32) architecture	2019-01-06 14:09:31 +01:00
arch.mk.xtensa	arc/xtensa: store the Xtensa overlay in the per-package DL_DIR	2018-04-02 15:59:30 +02:00
Config.in	arch: drop BR2_GCC_TARGET_CPU_REVISION option	2018-10-01 14:52:32 +02:00
Config.in.arc	arch/Config.in*: fix attributes order	2018-04-01 07:59:45 +02:00
Config.in.arm	arch/arm: add an armv8.3a core	2018-12-30 16:10:04 +01:00
Config.in.csky
Config.in.m68k	arch/Config.in*: fix attributes order	2018-04-01 07:59:45 +02:00
Config.in.microblaze
Config.in.mips	arch/mips: add (Marvell) Octeon III processor	2019-02-04 17:30:18 +01:00
Config.in.nios2
Config.in.or1k
Config.in.powerpc	arch/Config.in*: fix attributes order	2018-04-01 07:59:45 +02:00
Config.in.riscv	arch: add support for RISC-V 32-bit (riscv32) architecture	2019-01-06 14:09:31 +01:00
Config.in.sh	arch/Config.in*: fix attributes order	2018-04-01 07:59:45 +02:00
Config.in.sparc	arch/Config.in*: fix attributes order	2018-04-01 07:59:45 +02:00
Config.in.x86	arch: Add support for Westmere targets	2019-06-23 23:09:07 +02:00
Config.in.xtensa	arch/Config.in*: re-wrap help text	2018-04-01 08:00:13 +02:00