86eecc4606
This adds support the Xilinx ZCU106 development board. [Tested on the ES2 (Engineering Sample 2) version of the board] Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Cc: Joel Carlson <joelsoncarl@gmail.com> Tested-by: Joel Carlson <JoelsonCarl@gmail.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
53 lines
2.0 KiB
Diff
53 lines
2.0 KiB
Diff
From e5d72ed8339eb05285448aad3c89d21e4d18fd29 Mon Sep 17 00:00:00 2001
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From: Luca Ceresoli <luca@lucaceresoli.net>
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Date: Mon, 26 Feb 2018 09:40:34 +0100
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Subject: [PATCH] arm64: zynqmp: zcu106: fix SPL MMC booting
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The U-Boot SPL generated with the current zcu106 defconfig cannot boot
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from MMC:
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[...]
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U-Boot SPL 2018.01 (Feb 21 2018 - 17:47:14)
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EL Level: EL3
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Trying to boot from MMC1
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sdhci_transfer_data: Error detected in status(0x408020)!
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spl_load_image_fat_os: error reading image u-boot.bin, err - -2
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spl_load_image_fat: error reading image u-boot.img, err - -6
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SPL: failed to boot from all boot devices
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### ERROR ### Please RESET the board ###
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Fix by lowering the rpll value. The new value for the RPLL_CTRL
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register comes from the current psu_init_gpl.c from the HDF file at
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https://github.com/xilinx/hdf-examples/tree/01ad8ea5fd1989abf4ea5a072d019a16cb2bc546/zcu106-zynqmp
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(generated by Vivado v2017.4).
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RPLL and sdio1_ref clocks before and after this change:
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- Old values: RPLL 1.36 GHz, sdio1_ref 272 MHz
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- New values: RPLL 1.16 GHz, sdio1_ref 233 MHz
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Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
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Cc: Michal Simek <michal.simek@xilinx.com>
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Upstream-status: accepted upstream in a different form
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---
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board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
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index 4d18abe000ca..e6fa477e53e7 100644
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--- a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
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+++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
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@@ -10,7 +10,7 @@
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static unsigned long psu_pll_init_data(void)
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{
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psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4E2C62U);
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- psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00013C00U);
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+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
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psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
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psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
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psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
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--
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2.7.4
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