Mark Corbin ae99fa6d64 arch: add support for RISC-V 32-bit (riscv32) architecture ... This enables a riscv32 system to be built with a Buildroot generated toolchain (gcc >= 7.x, binutils >= 2.30, glibc only). This requires a custom version of glibc 2.26 from the riscv-glibc repository. Note that there are no tags in this repository, so the glibc version just consists of the 40 character commit id string. Thanks to Fabrice Bellard for pointing me towards the 32-bit glibc repository and for providing the necessary patch to get it to build. Signed-off-by: Mark Corbin <mark.corbin@embecosm.com> Reviewed-by: Matt Weber <matthew.weber@rockwellcollins.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>		2019-01-06 14:09:31 +01:00
..
arch.mk	arch: drop BR2_GCC_TARGET_CPU_REVISION option	2018-10-01 14:52:32 +02:00
arch.mk.riscv	arch: add support for RISC-V 32-bit (riscv32) architecture	2019-01-06 14:09:31 +01:00
arch.mk.xtensa	arc/xtensa: store the Xtensa overlay in the per-package DL_DIR	2018-04-02 15:59:30 +02:00
Config.in	arch: drop BR2_GCC_TARGET_CPU_REVISION option	2018-10-01 14:52:32 +02:00
Config.in.arc
Config.in.arm	arch/arm: add an armv8.3a core	2018-12-30 16:10:04 +01:00
Config.in.csky
Config.in.m68k
Config.in.microblaze
Config.in.mips
Config.in.nios2
Config.in.or1k
Config.in.powerpc
Config.in.riscv	arch: add support for RISC-V 32-bit (riscv32) architecture	2019-01-06 14:09:31 +01:00
Config.in.sh
Config.in.sparc
Config.in.x86
Config.in.xtensa