fc22c3ce40
This patch provides defconfig and basic support for Andes 45 series RISC-V architecture on AE350 platform. http://www.andestech.com/en/products-solutions/andeshape-platforms/ae350-axi-based-platform-pre-integrated-with-n25f-nx25f-a25-ax25/ Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Signed-off-by: Alan Kao <alankao@andestech.com> Reviewed-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Tested-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
275 lines
7.3 KiB
Plaintext
Executable File
275 lines
7.3 KiB
Plaintext
Executable File
/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "andestech,ae350";
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model = "andestech,ax45";
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aliases {
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uart0 = &serial0;
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spi0 = &spi;
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};
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chosen {
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bootargs = "console=ttyS0,38400n8 earlycon=sbi debug loglevel=7";
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stdout-path = "uart0:38400n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <60000000>;
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CPU0: cpu@0 {
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-1p1xdsp0p0";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv48";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-block-size = <64>;
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i-cache-line-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-line-size = <64>;
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next-level-cache = <&L2>;
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CPU0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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reg = <1>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-1p1xdsp0p0";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv48";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-block-size = <64>;
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i-cache-line-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-line-size = <64>;
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next-level-cache = <&L2>;
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CPU1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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reg = <2>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-1p1xdsp0p0";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv48";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-block-size = <64>;
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i-cache-line-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-line-size = <64>;
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next-level-cache = <&L2>;
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CPU2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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reg = <3>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-1p1xdsp0p0";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv48";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-block-size = <64>;
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i-cache-line-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-line-size = <64>;
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next-level-cache = <&L2>;
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CPU3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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L2: l2-cache@e0500000 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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reg = <0x00000000 0xe0500000 0x00000000 0x00001000>;
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andes,inst-prefetch = <3>;
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andes,data-prefetch = <3>;
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// The value format is <XRAMOCTL XRAMICTL>
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andes,tag-ram-ctl = <0 0>;
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andes,data-ram-ctl = <0 0>;
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};
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memory@0 {
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reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
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device_type = "memory";
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "andestech,riscv-ae350-soc", "simple-bus";
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ranges;
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plic0: interrupt-controller@e4000000 {
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compatible = "riscv,plic0";
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reg = <0x00000000 0xe4000000 0x00000000 0x02000000>;
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interrupts-extended = < &CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9 &CPU2_intc 11 &CPU2_intc 9 &CPU3_intc 11 &CPU3_intc 9>;
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interrupt-controller;
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#address-cells = <2>;
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#interrupt-cells = <2>;
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riscv,ndev = <71>;
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};
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plic1: interrupt-controller@e6400000 {
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compatible = "riscv,plic1";
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reg = <0x00000000 0xe6400000 0x00000000 0x00400000>;
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interrupts-extended = < &CPU0_intc 3 &CPU1_intc 3 &CPU2_intc 3 &CPU3_intc 3>;
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interrupt-controller;
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#address-cells = <2>;
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#interrupt-cells = <2>;
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riscv,ndev = <4>;
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};
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plmt0: plmt0@e6000000 {
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compatible = "riscv,plmt0";
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reg = <0x00000000 0xe6000000 0x00000000 0x00100000>;
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interrupts-extended = < &CPU0_intc 7 &CPU1_intc 7 &CPU2_intc 7 &CPU3_intc 7>;
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};
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spiclk: virt_100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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timer0: timer@f0400000 {
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compatible = "andestech,atcpit100";
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reg = <0x00000000 0xf0400000 0x00000000 0x00001000>;
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interrupts = <3 4>;
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interrupt-parent = <&plic0>;
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clock-frequency = <60000000>;
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};
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pwm: pwm@f0400000 {
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compatible = "andestech,atcpit100-pwm";
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reg = <0x00000000 0xf0400000 0x00000000 0x00001000>;
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interrupts = <3 4>;
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interrupt-parent = <&plic0>;
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clock-frequency = <60000000>;
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pwm-cells = <2>;
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};
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wdt: wdt@f0500000 {
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compatible = "andestech,atcwdt200";
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reg = <0x00000000 0xf0500000 0x00000000 0x00001000>;
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interrupts = <3 4>;
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interrupt-parent = <&plic0>;
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clock-frequency = <15000000>;
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};
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serial0: serial@f0300000 {
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compatible = "andestech,uart16550", "ns16550a";
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reg = <0x00000000 0xf0300000 0x00000000 0x00001000>;
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interrupts = <9 4>;
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interrupt-parent = <&plic0>;
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clock-frequency = <19660800>;
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reg-shift = <2>;
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reg-offset = <32>;
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no-loopback-test = <1>;
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};
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rtc0: rtc@f0600000 {
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compatible = "andestech,atcrtc100";
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reg = <0x00000000 0xf0600000 0x00000000 0x00001000>;
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interrupts = <1 4 2 4>;
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interrupt-parent = <&plic0>;
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wakeup-source;
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};
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gpio: gpio@f0700000 {
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compatible = "andestech,atcgpio100";
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reg = <0x00000000 0xf0700000 0x00000000 0x00001000>;
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interrupts = <7 4>;
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interrupt-parent = <&plic0>;
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wakeup-source;
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};
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mac0: mac@e0100000 {
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compatible = "andestech,atmac100";
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reg = <0x00000000 0xe0100000 0x00000000 0x00001000>;
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interrupts = <19 4>;
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interrupt-parent = <&plic0>;
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dma-coherent;
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};
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smu: smu@f0100000 {
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compatible = "andestech,atcsmu";
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reg = <0x00000000 0xf0100000 0x00000000 0x00001000>;
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};
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mmc0: mmc@f0e00000 {
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compatible = "andestech,atfsdc010";
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reg = <0x00000000 0xf0e00000 0x00000000 0x00001000>;
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interrupts = <18 4>;
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interrupt-parent = <&plic0>;
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clock-freq-min-max = <400000 100000000>;
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max-frequency = <100000000>;
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fifo-depth = <16>;
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cap-sd-highspeed;
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dma-coherent;
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};
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dma0: dma@f0c00000 {
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compatible = "andestech,atcdmac300";
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reg = <0x00000000 0xf0c00000 0x00000000 0x00001000>;
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interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
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interrupt-parent = <&plic0>;
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dma-channels = <8>;
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};
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lcd0: lcd@e0200000 {
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compatible = "andestech,atflcdc100";
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reg = <0x00000000 0xe0200000 0x00000000 0x00001000>;
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interrupts = <20 4>;
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interrupt-parent = <&plic0>;
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dma-coherent;
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};
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pmu: pmu {
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compatible = "riscv,andes-pmu";
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device_type = "pmu";
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};
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spi: spi@f0b00000 {
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compatible = "andestech,atcspi200";
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reg = <0x00000000 0xf0b00000 0x00000000 0x00001000>;
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interrupts = <4 4>;
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interrupt-parent = <&plic0>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <1>;
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clocks = <&spiclk>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0x00000000>;
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spi-max-frequency = <50000000>;
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spi-cpol;
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spi-cpha;
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};
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};
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};
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};
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