f82a65b15b
Alder Lake CPUs have AVX512 support disabled [0].
To prevent potential issues, remove the AVX512 support advertisement.
This puts Buildroot inline with the GCC options [1].
[0]: https://www.intel.com/content/www/us/en/support/articles/000089918/processors.html
[1]: https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
Fixes: e7b94130 ("arch/Config.in.x86: add sapphirerapids, alderlake, rocketlake")
Signed-off-by: Vincent Fazio <vfazio@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
648 lines
19 KiB
Plaintext
648 lines
19 KiB
Plaintext
# i386/x86_64 cpu features
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config BR2_X86_CPU_HAS_MMX
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bool
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config BR2_X86_CPU_HAS_3DNOW
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bool
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config BR2_X86_CPU_HAS_SSE
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bool
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config BR2_X86_CPU_HAS_SSE2
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bool
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config BR2_X86_CPU_HAS_SSE3
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bool
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config BR2_X86_CPU_HAS_SSSE3
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bool
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config BR2_X86_CPU_HAS_SSE4
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bool
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config BR2_X86_CPU_HAS_SSE42
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bool
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config BR2_X86_CPU_HAS_AVX
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bool
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config BR2_X86_CPU_HAS_AVX2
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bool
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config BR2_X86_CPU_HAS_AVX512
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bool
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# This list of CPU architecture variant is (loosely) ordered according
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# to the gcc documentation at
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# https://gcc.gnu.org/onlinedocs/gcc-11.2.0/gcc/x86-Options.html
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choice
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prompt "Target Architecture Variant"
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default BR2_x86_i586 if BR2_i386
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depends on BR2_i386 || BR2_x86_64
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help
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Specific CPU variant to use
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config BR2_x86_i486
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bool "i486"
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depends on !BR2_x86_64
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config BR2_x86_i586
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bool "i586"
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depends on !BR2_x86_64
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config BR2_x86_x1000
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bool "x1000"
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depends on !BR2_x86_64
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help
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The Intel X1000 is a Pentium class microprocessor in the
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Quark (sub-Atom) Product Line. The X1000 has a bug on the
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lock prefix requiring that prefix must be stripped at build
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time.
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See https://en.wikipedia.org/wiki/Intel_Quark
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config BR2_x86_i686
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bool "i686"
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depends on !BR2_x86_64
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config BR2_x86_pentiumpro
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bool "pentium pro"
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depends on !BR2_x86_64
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config BR2_x86_pentium_mmx
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bool "pentium MMX"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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config BR2_x86_pentium_m
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bool "pentium mobile"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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config BR2_x86_pentium2
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bool "pentium2"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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config BR2_x86_pentium3
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bool "pentium3"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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config BR2_x86_pentium4
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bool "pentium4"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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config BR2_x86_prescott
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bool "prescott"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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config BR2_x86_x86_64
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bool "x86-64"
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depends on BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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help
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This option corresponds to -march=x86-64, documented as a
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"Generic CPU with 64-bit extensions" by the GCC
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documentation. It is a 64-bit CPU with MMX, SSE and SSE2
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support.
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config BR2_x86_x86_64_v2
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bool "x86-64-v2"
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depends on BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
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help
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This option corresponds to the x86-64-v2 micro-architecture
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level, as defined by the x86-64 psABI document, see
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https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex.
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It is close to the Nehalem CPU architecture, and is
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applicable for CPUs that support CMPXCHG16B, LAHF-SAHF,
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POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3.
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config BR2_x86_x86_64_v3
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bool "x86-64-v3"
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depends on BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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select BR2_X86_CPU_HAS_AVX2
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
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help
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This option corresponds to the x86-64-v3 micro-architecture
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level, as defined by the x86-64 psABI document, see
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https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex.
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It is close to the Haswell CPU architecture, and is
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applicable for CPUs that support all of x86-64-v2 plus AVX,
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AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE.
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config BR2_x86_x86_64_v4
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bool "x86-64-v4"
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depends on BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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select BR2_X86_CPU_HAS_AVX2
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select BR2_X86_CPU_HAS_AVX512
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
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help
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This option corresponds to the x86-64-v4 micro-architecture
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level, as defined by the x86-64 psABI document, see
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https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex.
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It is applicable for CPUs that support all of x86-64-v3 plus
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AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL.
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config BR2_x86_nocona
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bool "nocona"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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config BR2_x86_core2
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bool "core2"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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config BR2_x86_corei7
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bool "corei7"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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help
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This option is deprecated. Since gcc 4.9, the gcc option
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"nehalem" is preferred. Use BR2_x86_nehalem instead.
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config BR2_x86_nehalem
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bool "nehalem"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
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config BR2_x86_westmere
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bool "westmere"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
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config BR2_x86_corei7_avx
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bool "corei7-avx"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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help
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This option is deprecated. Since gcc 4.9, the gcc option
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"sandybridge" is preferred. Use BR2_x86_sandybridge instead.
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config BR2_x86_sandybridge
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bool "sandybridge"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
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config BR2_x86_core_avx2
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bool "core-avx2"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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select BR2_X86_CPU_HAS_AVX2
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help
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This option is deprecated. Since gcc 4.9, the gcc option
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"haswell" is preferred. Use BR2_x86_haswell instead.
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config BR2_x86_haswell
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bool "haswell"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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select BR2_X86_CPU_HAS_AVX2
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
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config BR2_x86_broadwell
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bool "broadwell"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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select BR2_X86_CPU_HAS_AVX2
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
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config BR2_x86_skylake
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bool "skylake"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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select BR2_X86_CPU_HAS_AVX2
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
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config BR2_x86_atom
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bool "atom"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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help
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This option is deprecated. Since gcc 4.9, the gcc option
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"bonnell" is preferred. Use BR2_x86_bonnell instead.
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config BR2_x86_bonnell
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bool "bonnell"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
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config BR2_x86_silvermont
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bool "silvermont"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
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config BR2_x86_goldmont
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bool "goldmont"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
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config BR2_x86_goldmont_plus
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bool "goldmont-plus"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
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config BR2_x86_tremont
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bool "tremont"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
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config BR2_x86_skylake_avx512
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bool "skylake-avx512"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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select BR2_X86_CPU_HAS_AVX2
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select BR2_X86_CPU_HAS_AVX512
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
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config BR2_x86_cannonlake
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bool "cannonlake"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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select BR2_X86_CPU_HAS_AVX2
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select BR2_X86_CPU_HAS_AVX512
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
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config BR2_x86_icelake_client
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bool "icelake-client"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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select BR2_X86_CPU_HAS_AVX2
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select BR2_X86_CPU_HAS_AVX512
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
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config BR2_x86_icelake_server
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bool "icelake-server"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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select BR2_X86_CPU_HAS_AVX2
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select BR2_X86_CPU_HAS_AVX512
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
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config BR2_x86_cascadelake
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bool "cascadelake"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
select BR2_X86_CPU_HAS_AVX
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
select BR2_X86_CPU_HAS_AVX512
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
|
|
config BR2_x86_cooperlake
|
|
bool "cooperlake"
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_SSE
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
select BR2_X86_CPU_HAS_AVX
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
select BR2_X86_CPU_HAS_AVX512
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_10
|
|
config BR2_x86_tigerlake
|
|
bool "tigerlake"
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_SSE
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
select BR2_X86_CPU_HAS_AVX
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
select BR2_X86_CPU_HAS_AVX512
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
|
|
config BR2_x86_sapphirerapids
|
|
bool "sapphirerapids"
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_SSE
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
select BR2_X86_CPU_HAS_AVX
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
select BR2_X86_CPU_HAS_AVX512
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
|
|
config BR2_x86_alderlake
|
|
bool "alderlake"
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_SSE
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
select BR2_X86_CPU_HAS_AVX
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
|
|
config BR2_x86_rocketlake
|
|
bool "rocketlake"
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_SSE
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
select BR2_X86_CPU_HAS_AVX
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
select BR2_X86_CPU_HAS_AVX512
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
|
|
config BR2_x86_k6
|
|
bool "k6"
|
|
depends on !BR2_x86_64
|
|
select BR2_X86_CPU_HAS_MMX
|
|
config BR2_x86_k6_2
|
|
bool "k6-2"
|
|
depends on !BR2_x86_64
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_3DNOW
|
|
config BR2_x86_athlon
|
|
bool "athlon"
|
|
depends on !BR2_x86_64
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_3DNOW
|
|
config BR2_x86_athlon_4
|
|
bool "athlon-4"
|
|
depends on !BR2_x86_64
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_SSE
|
|
select BR2_X86_CPU_HAS_3DNOW
|
|
config BR2_x86_opteron
|
|
bool "opteron"
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_SSE
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
config BR2_x86_opteron_sse3
|
|
bool "opteron w/ SSE3"
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_SSE
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
config BR2_x86_barcelona
|
|
bool "barcelona"
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_SSE
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
config BR2_x86_jaguar
|
|
bool "jaguar"
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_SSE
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
config BR2_x86_steamroller
|
|
bool "steamroller"
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_SSE
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
config BR2_x86_geode
|
|
bool "geode (no mmx)"
|
|
depends on !BR2_x86_64
|
|
help
|
|
For several variant of geode which have not MMX support.
|
|
See https://en.wikipedia.org/wiki/Geode_%28processor%29 to
|
|
determine if your particular Geode processor supports MMX or
|
|
not.
|
|
config BR2_x86_geode_mmx
|
|
bool "geode (with mmx)"
|
|
depends on !BR2_x86_64
|
|
select BR2_X86_CPU_HAS_MMX
|
|
help
|
|
For several variant of geode which have MMX support.
|
|
See https://en.wikipedia.org/wiki/Geode_%28processor%29 to
|
|
determine if your particular Geode processor supports MMX or
|
|
not.
|
|
config BR2_x86_c3
|
|
bool "Via/Cyrix C3 (Samuel/Ezra cores)"
|
|
depends on !BR2_x86_64
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_3DNOW
|
|
config BR2_x86_c32
|
|
bool "Via C3-2 (Nehemiah cores)"
|
|
depends on !BR2_x86_64
|
|
select BR2_X86_CPU_HAS_MMX
|
|
select BR2_X86_CPU_HAS_SSE
|
|
config BR2_x86_winchip_c6
|
|
bool "IDT Winchip C6"
|
|
depends on !BR2_x86_64
|
|
select BR2_X86_CPU_HAS_MMX
|
|
config BR2_x86_winchip2
|
|
bool "IDT Winchip 2"
|
|
depends on !BR2_x86_64
|
|
select BR2_X86_CPU_HAS_MMX
|
|
endchoice
|
|
|
|
config BR2_ARCH
|
|
default "i486" if BR2_x86_i486
|
|
default "i586" if BR2_x86_i586
|
|
default "i586" if BR2_x86_x1000
|
|
default "i586" if BR2_x86_pentium_mmx
|
|
default "i586" if BR2_x86_geode
|
|
default "i586" if BR2_x86_c3
|
|
default "i686" if BR2_x86_c32
|
|
default "i586" if BR2_x86_winchip_c6
|
|
default "i586" if BR2_x86_winchip2
|
|
# We use the property of Kconfig that the first match of a
|
|
# list of default will be chosen. So the following entry will
|
|
# not match for all BR2_i386=y configurations, but only the
|
|
# ones that didn't match any of the previous cases (i486,
|
|
# i586).
|
|
default "i686" if BR2_i386
|
|
default "x86_64" if BR2_x86_64
|
|
|
|
config BR2_NORMALIZED_ARCH
|
|
default "i386" if !BR2_x86_64
|
|
default "x86_64" if BR2_x86_64
|
|
|
|
config BR2_ENDIAN
|
|
default "LITTLE"
|
|
|
|
config BR2_GCC_TARGET_ARCH
|
|
default "i486" if BR2_x86_i486
|
|
default "i586" if BR2_x86_i586
|
|
default "i586" if BR2_x86_x1000
|
|
default "pentium-mmx" if BR2_x86_pentium_mmx
|
|
default "i686" if BR2_x86_i686
|
|
default "pentiumpro" if BR2_x86_pentiumpro
|
|
default "pentium-m" if BR2_x86_pentium_m
|
|
default "pentium2" if BR2_x86_pentium2
|
|
default "pentium3" if BR2_x86_pentium3
|
|
default "pentium4" if BR2_x86_pentium4
|
|
default "prescott" if BR2_x86_prescott
|
|
default "x86-64" if BR2_x86_x86_64
|
|
default "x86-64-v2" if BR2_x86_x86_64_v2
|
|
default "x86-64-v3" if BR2_x86_x86_64_v3
|
|
default "x86-64-v4" if BR2_x86_x86_64_v4
|
|
default "nocona" if BR2_x86_nocona
|
|
default "core2" if BR2_x86_core2
|
|
default "corei7" if BR2_x86_corei7
|
|
default "nehalem" if BR2_x86_nehalem
|
|
default "corei7-avx" if BR2_x86_corei7_avx
|
|
default "sandybridge" if BR2_x86_sandybridge
|
|
default "core-avx2" if BR2_x86_core_avx2
|
|
default "haswell" if BR2_x86_haswell
|
|
default "broadwell" if BR2_x86_broadwell
|
|
default "skylake" if BR2_x86_skylake
|
|
default "atom" if BR2_x86_atom
|
|
default "bonnell" if BR2_x86_bonnell
|
|
default "westmere" if BR2_x86_westmere
|
|
default "silvermont" if BR2_x86_silvermont
|
|
default "goldmont" if BR2_x86_goldmont
|
|
default "goldmont-plus" if BR2_x86_goldmont_plus
|
|
default "tremont" if BR2_x86_tremont
|
|
default "skylake-avx512" if BR2_x86_skylake_avx512
|
|
default "cannonlake" if BR2_x86_cannonlake
|
|
default "icelake-client" if BR2_x86_icelake_client
|
|
default "icelake-server" if BR2_x86_icelake_server
|
|
default "cascadelake" if BR2_x86_cascadelake
|
|
default "cooperlake" if BR2_x86_cooperlake
|
|
default "tigerlake" if BR2_x86_tigerlake
|
|
default "sapphirerapids" if BR2_x86_sapphirerapids
|
|
default "alderlake" if BR2_x86_alderlake
|
|
default "rocketlake" if BR2_x86_rocketlake
|
|
default "k8" if BR2_x86_opteron
|
|
default "k8-sse3" if BR2_x86_opteron_sse3
|
|
default "barcelona" if BR2_x86_barcelona
|
|
default "btver2" if BR2_x86_jaguar
|
|
default "bdver3" if BR2_x86_steamroller
|
|
default "k6" if BR2_x86_k6
|
|
default "k6-2" if BR2_x86_k6_2
|
|
default "athlon" if BR2_x86_athlon
|
|
default "athlon-4" if BR2_x86_athlon_4
|
|
default "winchip-c6" if BR2_x86_winchip_c6
|
|
default "winchip2" if BR2_x86_winchip2
|
|
default "c3" if BR2_x86_c3
|
|
default "c3-2" if BR2_x86_c32
|
|
default "geode" if BR2_x86_geode
|
|
|
|
config BR2_READELF_ARCH_NAME
|
|
default "Intel 80386" if BR2_i386
|
|
default "Advanced Micro Devices X86-64" if BR2_x86_64
|
|
|
|
# vim: ft=kconfig
|
|
# -*- mode:kconfig; -*-
|