Esben Haabendal 39a9d01819 arch: Add support for Westmere targets ... The westmere line of x86_64 targets lies between nehalem (corei7) and sandybridge (corei7-avx). Allowing use of -march=westmere enables use of AES instruction set on these targets. Signed-off-by: Esben Haabendal <esben@geanix.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com> (cherry picked from commit 97651ce275) Signed-off-by: Peter Korsgaard <peter@korsgaard.com>		2019-06-23 23:08:56 +02:00
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arch.mk
arch.mk.riscv
arch.mk.xtensa
Config.in	arch: add support for Andes 32-bit (nds32)	2019-04-17 09:03:37 +02:00
Config.in.arc
Config.in.arm
Config.in.csky
Config.in.m68k
Config.in.microblaze
Config.in.mips	arch/mips: add (Marvell) Octeon III processor	2019-02-04 17:30:18 +01:00
Config.in.nds32	package/binutils: fix build error due to architecture name is incomplete	2019-04-20 16:16:39 +02:00
Config.in.nios2
Config.in.or1k
Config.in.powerpc	arch/Config.in.powerpc: remove unused gcc target abi options for powerpc	2019-06-01 14:26:29 +02:00
Config.in.riscv
Config.in.sh
Config.in.sparc
Config.in.x86	arch: Add support for Westmere targets	2019-06-23 23:08:56 +02:00
Config.in.xtensa