eeace1cc13
In the face of the vast amount of x86-64 CPU architecture variants, Linux distributions have worked together to define "micro-architecture levels" in the x86-64 psABI, called x86-64-v2, x86-64-v3 and x86-64-v4. They standardize a set of CPU features, and GCC since its version 11.x has support for these micro-architecture levels as -march= options. It makes sense to support them in Buildroot, especially for those who want to build toolchains that aim at targeting a reasonably broad family of x86-64 processors. It only really makes sense to use as 64-bit CPUs, and not as 32-bit ones, so we guard them behind BR2_x86_64. More details: https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex https://developers.redhat.com/blog/2021/01/05/building-red-hat-enterprise-linux-9-for-the-x86-64-v2-microarchitecture-level https://www.phoronix.com/scan.php?page=news_item&px=GCC-11-x86-64-Feature-Levels https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=59482fa1e7243bd905c7e27c92ae2b89c79fff87 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> [yann.morin.1998@free.fr: - they are x86-64-only CPUs - add gcc commit URL ] Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
388 lines
11 KiB
Plaintext
388 lines
11 KiB
Plaintext
# i386/x86_64 cpu features
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config BR2_X86_CPU_HAS_MMX
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bool
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config BR2_X86_CPU_HAS_3DNOW
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bool
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config BR2_X86_CPU_HAS_SSE
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bool
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config BR2_X86_CPU_HAS_SSE2
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bool
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config BR2_X86_CPU_HAS_SSE3
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bool
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config BR2_X86_CPU_HAS_SSSE3
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bool
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config BR2_X86_CPU_HAS_SSE4
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bool
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config BR2_X86_CPU_HAS_SSE42
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bool
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config BR2_X86_CPU_HAS_AVX
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bool
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config BR2_X86_CPU_HAS_AVX2
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bool
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choice
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prompt "Target Architecture Variant"
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default BR2_x86_i586 if BR2_i386
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depends on BR2_i386 || BR2_x86_64
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help
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Specific CPU variant to use
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config BR2_x86_i486
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bool "i486"
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depends on !BR2_x86_64
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config BR2_x86_i586
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bool "i586"
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depends on !BR2_x86_64
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config BR2_x86_x1000
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bool "x1000"
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depends on !BR2_x86_64
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help
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The Intel X1000 is a Pentium class microprocessor in the
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Quark (sub-Atom) Product Line. The X1000 has a bug on the
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lock prefix requiring that prefix must be stripped at build
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time.
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See https://en.wikipedia.org/wiki/Intel_Quark
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config BR2_x86_i686
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bool "i686"
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depends on !BR2_x86_64
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config BR2_x86_pentiumpro
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bool "pentium pro"
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depends on !BR2_x86_64
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config BR2_x86_pentium_mmx
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bool "pentium MMX"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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config BR2_x86_pentium_m
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bool "pentium mobile"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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config BR2_x86_pentium2
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bool "pentium2"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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config BR2_x86_pentium3
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bool "pentium3"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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config BR2_x86_pentium4
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bool "pentium4"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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config BR2_x86_prescott
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bool "prescott"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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config BR2_x86_x86_64
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bool "x86-64"
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depends on BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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help
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This option corresponds to -march=x86-64, documented as a
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"Generic CPU with 64-bit extensions" by the GCC
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documentation. It is a 64-bit CPU with MMX, SSE and SSE2
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support.
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config BR2_x86_x86_64_v2
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bool "x86-64-v2"
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depends on BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
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help
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This option corresponds to the x86-64-v2 micro-architecture
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level, as defined by the x86-64 psABI document, see
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https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex.
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It is close to the Nehalem CPU architecture, and is
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applicable for CPUs that support CMPXCHG16B, LAHF-SAHF,
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POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3.
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config BR2_x86_x86_64_v3
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bool "x86-64-v3"
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depends on BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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select BR2_X86_CPU_HAS_AVX2
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
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help
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This option corresponds to the x86-64-v3 micro-architecture
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level, as defined by the x86-64 psABI document, see
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https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex.
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It is close to the Haswell CPU architecture, and is
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applicable for CPUs that support all of x86-64-v2 plus AVX,
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AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE.
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config BR2_x86_x86_64_v4
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bool "x86-64-v4"
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depends on BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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select BR2_X86_CPU_HAS_AVX2
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
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help
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This option corresponds to the x86-64-v4 micro-architecture
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level, as defined by the x86-64 psABI document, see
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https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex.
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It is applicable for CPUs that support all of x86-64-v3 plus
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AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL.
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config BR2_x86_nocona
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bool "nocona"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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config BR2_x86_core2
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bool "core2"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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config BR2_x86_corei7
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bool "corei7"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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config BR2_x86_westmere
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bool "westmere"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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config BR2_x86_corei7_avx
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bool "corei7-avx"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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config BR2_x86_core_avx2
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bool "core-avx2"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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select BR2_X86_CPU_HAS_AVX
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select BR2_X86_CPU_HAS_AVX2
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config BR2_x86_atom
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bool "atom"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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config BR2_x86_silvermont
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bool "silvermont"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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config BR2_x86_k6
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bool "k6"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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config BR2_x86_k6_2
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bool "k6-2"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_3DNOW
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config BR2_x86_athlon
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bool "athlon"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_3DNOW
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config BR2_x86_athlon_4
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bool "athlon-4"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_3DNOW
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config BR2_x86_opteron
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bool "opteron"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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config BR2_x86_opteron_sse3
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bool "opteron w/ SSE3"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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config BR2_x86_barcelona
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bool "barcelona"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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config BR2_x86_jaguar
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bool "jaguar"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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config BR2_x86_steamroller
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bool "steamroller"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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config BR2_x86_geode
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bool "geode"
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# Don't include MMX support because there several variant of geode
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# processor, some with MMX support, some without.
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# See: http://en.wikipedia.org/wiki/Geode_%28processor%29
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depends on !BR2_x86_64
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config BR2_x86_c3
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bool "Via/Cyrix C3 (Samuel/Ezra cores)"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_3DNOW
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config BR2_x86_c32
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bool "Via C3-2 (Nehemiah cores)"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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config BR2_x86_winchip_c6
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bool "IDT Winchip C6"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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config BR2_x86_winchip2
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bool "IDT Winchip 2"
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depends on !BR2_x86_64
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select BR2_X86_CPU_HAS_MMX
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endchoice
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config BR2_ARCH
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default "i486" if BR2_x86_i486
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default "i586" if BR2_x86_i586
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default "i586" if BR2_x86_x1000
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default "i586" if BR2_x86_pentium_mmx
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default "i586" if BR2_x86_geode
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default "i586" if BR2_x86_c3
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default "i686" if BR2_x86_c32
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default "i586" if BR2_x86_winchip_c6
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default "i586" if BR2_x86_winchip2
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default "i686" if BR2_x86_i686
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default "i686" if BR2_x86_pentium2
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default "i686" if BR2_x86_pentium3
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default "i686" if BR2_x86_pentium4
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default "i686" if BR2_x86_pentium_m
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default "i686" if BR2_x86_pentiumpro
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default "i686" if BR2_x86_prescott
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default "i686" if BR2_x86_nocona && BR2_i386
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default "i686" if BR2_x86_core2 && BR2_i386
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default "i686" if BR2_x86_corei7 && BR2_i386
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default "i686" if BR2_x86_westmere && BR2_i386
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default "i686" if BR2_x86_corei7_avx && BR2_i386
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default "i686" if BR2_x86_core_avx2 && BR2_i386
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default "i686" if BR2_x86_atom && BR2_i386
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default "i686" if BR2_x86_silvermont && BR2_i386
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default "i686" if BR2_x86_opteron && BR2_i386
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default "i686" if BR2_x86_opteron_sse3 && BR2_i386
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default "i686" if BR2_x86_barcelona && BR2_i386
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default "i686" if BR2_x86_jaguar && BR2_i386
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default "i686" if BR2_x86_steamroller && BR2_i386
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default "i686" if BR2_x86_k6
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default "i686" if BR2_x86_k6_2
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default "i686" if BR2_x86_athlon
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default "i686" if BR2_x86_athlon_4
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default "x86_64" if BR2_x86_64
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config BR2_ENDIAN
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default "LITTLE"
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config BR2_GCC_TARGET_ARCH
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default "i486" if BR2_x86_i486
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default "i586" if BR2_x86_i586
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default "i586" if BR2_x86_x1000
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default "pentium-mmx" if BR2_x86_pentium_mmx
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default "i686" if BR2_x86_i686
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default "pentiumpro" if BR2_x86_pentiumpro
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default "pentium-m" if BR2_x86_pentium_m
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default "pentium2" if BR2_x86_pentium2
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default "pentium3" if BR2_x86_pentium3
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default "pentium4" if BR2_x86_pentium4
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default "prescott" if BR2_x86_prescott
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default "x86-64" if BR2_x86_x86_64
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default "x86-64-v2" if BR2_x86_x86_64_v2
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default "x86-64-v3" if BR2_x86_x86_64_v3
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default "x86-64-v4" if BR2_x86_x86_64_v4
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default "nocona" if BR2_x86_nocona
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default "core2" if BR2_x86_core2
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default "corei7" if BR2_x86_corei7
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default "corei7-avx" if BR2_x86_corei7_avx
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default "core-avx2" if BR2_x86_core_avx2
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default "atom" if BR2_x86_atom
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default "westmere" if BR2_x86_westmere
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default "silvermont" if BR2_x86_silvermont
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default "k8" if BR2_x86_opteron
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default "k8-sse3" if BR2_x86_opteron_sse3
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default "barcelona" if BR2_x86_barcelona
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default "btver2" if BR2_x86_jaguar
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default "bdver3" if BR2_x86_steamroller
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default "k6" if BR2_x86_k6
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default "k6-2" if BR2_x86_k6_2
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default "athlon" if BR2_x86_athlon
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default "athlon-4" if BR2_x86_athlon_4
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default "winchip-c6" if BR2_x86_winchip_c6
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default "winchip2" if BR2_x86_winchip2
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default "c3" if BR2_x86_c3
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default "c3-2" if BR2_x86_c32
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default "geode" if BR2_x86_geode
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config BR2_READELF_ARCH_NAME
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default "Intel 80386" if BR2_i386
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default "Advanced Micro Devices X86-64" if BR2_x86_64
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# vim: ft=kconfig
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# -*- mode:kconfig; -*-
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