cbd91e89e4
The generic extension set 'G' is realy a base with the minimal set of extensions needed to be comfortable (but not required) to run a linux-bassed system. Similarly, we consider the custom to be about the custom set of features (not about a custom core implementing such a set). As such, we allow that a core with the G set can have futher extensions without requiring it to be configured as a custom set. We drop the intermediate symbols with the prompts, and move the prompts to the previously hidden symbols, and add a prompt for the I set. This alows one to clearly see what the generic set is about, without having to delve into the help and hunt the list of selected symbol. Note however that the G set implies Zicsr and Zifencei, but we have no prompt for thos two, because in Buildroot, we assume that they are mandatory and always present, like the I set (which they previously were part of). Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com> [yann.morin.1998@free.fr: - drop the intermediate symbols - move prompt to previously hidden symbols - add symbol for I - update defconfigs - reword the commit log accordingly ] Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
129 lines
2.8 KiB
Plaintext
129 lines
2.8 KiB
Plaintext
# RISC-V CPU ISA extensions.
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choice
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prompt "Target Architecture Variant"
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default BR2_riscv_g
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config BR2_riscv_g
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bool "General purpose (G)"
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select BR2_RISCV_ISA_RVI
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select BR2_RISCV_ISA_RVM
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select BR2_RISCV_ISA_RVA
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select BR2_RISCV_ISA_RVF
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select BR2_RISCV_ISA_RVD
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help
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General purpose (G) is equivalent to IMAFD.
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config BR2_riscv_custom
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bool "Custom architecture"
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select BR2_RISCV_ISA_RVI
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endchoice
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comment "Instruction Set Extensions"
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config BR2_RISCV_ISA_RVI
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bool "Base Integer (I)"
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config BR2_RISCV_ISA_RVM
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bool "Integer Multiplication and Division (M)"
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config BR2_RISCV_ISA_RVA
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bool "Atomic Instructions (A)"
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config BR2_RISCV_ISA_RVF
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bool "Single-precision Floating-point (F)"
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config BR2_RISCV_ISA_RVD
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bool "Double-precision Floating-point (D)"
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depends on BR2_RISCV_ISA_RVF
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config BR2_RISCV_ISA_RVC
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bool "Compressed Instructions (C)"
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config BR2_RISCV_ISA_RVV
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bool "Vector Instructions (V)"
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
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choice
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prompt "Target Architecture Size"
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default BR2_RISCV_64
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config BR2_RISCV_32
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bool "32-bit"
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select BR2_USE_MMU
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config BR2_RISCV_64
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bool "64-bit"
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select BR2_ARCH_IS_64
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endchoice
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config BR2_RISCV_USE_MMU
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bool "MMU support"
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default y
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depends on BR2_RISCV_64
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select BR2_USE_MMU
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help
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Enable this option if your RISC-V core has a MMU (Memory
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Management Unit).
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choice
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prompt "Target ABI"
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default BR2_RISCV_ABI_ILP32D if !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
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default BR2_RISCV_ABI_ILP32F if !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
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default BR2_RISCV_ABI_ILP32 if !BR2_ARCH_IS_64
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default BR2_RISCV_ABI_LP64D if BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
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default BR2_RISCV_ABI_LP64F if BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
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default BR2_RISCV_ABI_LP64 if BR2_ARCH_IS_64
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config BR2_RISCV_ABI_ILP32
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bool "ilp32"
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depends on !BR2_ARCH_IS_64
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config BR2_RISCV_ABI_ILP32F
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bool "ilp32f"
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depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
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config BR2_RISCV_ABI_ILP32D
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bool "ilp32d"
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depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
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config BR2_RISCV_ABI_LP64
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bool "lp64"
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depends on BR2_ARCH_IS_64
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config BR2_RISCV_ABI_LP64F
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bool "lp64f"
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depends on BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
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depends on BR2_USE_MMU
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config BR2_RISCV_ABI_LP64D
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bool "lp64d"
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depends on BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
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endchoice
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config BR2_ARCH
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default "riscv32" if !BR2_ARCH_IS_64
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default "riscv64" if BR2_ARCH_IS_64
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config BR2_NORMALIZED_ARCH
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default "riscv"
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config BR2_ENDIAN
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default "LITTLE"
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config BR2_GCC_TARGET_ABI
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default "ilp32" if BR2_RISCV_ABI_ILP32
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default "ilp32f" if BR2_RISCV_ABI_ILP32F
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default "ilp32d" if BR2_RISCV_ABI_ILP32D
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default "lp64" if BR2_RISCV_ABI_LP64
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default "lp64f" if BR2_RISCV_ABI_LP64F
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default "lp64d" if BR2_RISCV_ABI_LP64D
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config BR2_READELF_ARCH_NAME
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default "RISC-V"
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# vim: ft=kconfig
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# -*- mode:kconfig; -*-
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