80e4060908
The fuzzy generic x86 variant doesn't make much sense in the context of Buildroot, and the recent change to use -march instead of -mtune broke it. From the GCC manual: https://gcc.gnu.org/onlinedocs/gcc-4.9.2/gcc/i386-and-x86-64-Options.html#i386-and-x86-64-Options: -mtune=cpu-type Tune to cpu-type everything applicable about the generated code, except for the ABI and the set of available instructions. While picking a specific cpu-type schedules things appropriately for that particular chip, the compiler does not generate any code that cannot run on the default machine type unless you use a -march=cpu-type option. For example, if GCC is configured for i686-pc-linux-gnu then -mtune=pentium4 generates code that is tuned for Pentium 4 but still runs on i686 machines. The choices for cpu-type are the same as for -march. In addition, -mtune supports 2 extra choices for cpu-type: ‘generic’ Produce code optimized for the most common IA32/AMD64/EM64T processors. If you know the CPU on which your code will run, then you should use the corresponding -mtune or -march option instead of -mtune=generic. But, if you do not know exactly what CPU users of your application will have, then you should use this option. As new processors are deployed in the marketplace, the behavior of this option will change. Therefore, if you upgrade to a newer version of GCC, code generation controlled by this option will change to reflect the processors that are most common at the time that version of GCC is released. There is no -march=generic option because -march indicates the instruction set the compiler can use, and there is no generic instruction set applicable to all processors. In contrast, -mtune indicates the processor (or, in this case, collection of processors) for which the code is optimized. Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
233 lines
6.1 KiB
Plaintext
233 lines
6.1 KiB
Plaintext
# i386/x86_64 cpu features
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config BR2_X86_CPU_HAS_MMX
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bool
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config BR2_X86_CPU_HAS_SSE
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bool
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config BR2_X86_CPU_HAS_SSE2
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bool
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config BR2_X86_CPU_HAS_SSE3
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bool
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config BR2_X86_CPU_HAS_SSSE3
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bool
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config BR2_X86_CPU_HAS_SSE4
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bool
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config BR2_X86_CPU_HAS_SSE42
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bool
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choice
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prompt "Target Architecture Variant"
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depends on BR2_i386 || BR2_x86_64
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default BR2_x86_i586 if BR2_i386
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help
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Specific CPU variant to use
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config BR2_x86_i386
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bool "i386"
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depends on !BR2_x86_64
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config BR2_x86_i486
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bool "i486"
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depends on !BR2_x86_64
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config BR2_x86_i586
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bool "i586"
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depends on !BR2_x86_64
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config BR2_x86_i686
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bool "i686"
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depends on !BR2_x86_64
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config BR2_x86_pentiumpro
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bool "pentium pro"
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depends on !BR2_x86_64
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config BR2_x86_pentium_mmx
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bool "pentium MMX"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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config BR2_x86_pentium_m
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bool "pentium mobile"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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depends on !BR2_x86_64
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config BR2_x86_pentium2
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bool "pentium2"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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config BR2_x86_pentium3
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bool "pentium3"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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depends on !BR2_x86_64
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config BR2_x86_pentium4
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bool "pentium4"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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depends on !BR2_x86_64
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config BR2_x86_prescott
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bool "prescott"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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depends on !BR2_x86_64
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config BR2_x86_nocona
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bool "nocona"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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config BR2_x86_core2
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bool "core2"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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config BR2_x86_corei7
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bool "corei7"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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config BR2_x86_atom
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bool "atom"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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config BR2_x86_k6
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bool "k6"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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config BR2_x86_k6_2
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bool "k6-2"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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config BR2_x86_athlon
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bool "athlon"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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config BR2_x86_athlon_4
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bool "athlon-4"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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depends on !BR2_x86_64
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config BR2_x86_opteron
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bool "opteron"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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config BR2_x86_opteron_sse3
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bool "opteron w/ SSE3"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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config BR2_x86_barcelona
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bool "barcelona"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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config BR2_x86_jaguar
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bool "jaguar"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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select BR2_X86_CPU_HAS_SSE4
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select BR2_X86_CPU_HAS_SSE42
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config BR2_x86_geode
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bool "geode"
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# Don't include MMX support because there several variant of geode
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# processor, some with MMX support, some without.
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# See: http://en.wikipedia.org/wiki/Geode_%28processor%29
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depends on !BR2_x86_64
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config BR2_x86_c3
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bool "Via/Cyrix C3 (Samuel/Ezra cores)"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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config BR2_x86_c32
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bool "Via C3-2 (Nehemiah cores)"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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depends on !BR2_x86_64
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config BR2_x86_winchip_c6
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bool "IDT Winchip C6"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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config BR2_x86_winchip2
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bool "IDT Winchip 2"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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endchoice
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config BR2_ARCH
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default "i386" if BR2_x86_i386
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default "i486" if BR2_x86_i486
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default "i586" if BR2_x86_i586
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default "i586" if BR2_x86_pentium_mmx
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default "i586" if BR2_x86_geode
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default "i586" if BR2_x86_c3
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default "i686" if BR2_x86_c32
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default "i586" if BR2_x86_winchip_c6
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default "i586" if BR2_x86_winchip2
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default "i686" if BR2_x86_i686
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default "i686" if BR2_x86_pentium2
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default "i686" if BR2_x86_pentium3
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default "i686" if BR2_x86_pentium4
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default "i686" if BR2_x86_pentium_m
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default "i686" if BR2_x86_pentiumpro
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default "i686" if BR2_x86_prescott
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default "i686" if BR2_x86_nocona && BR2_i386
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default "i686" if BR2_x86_core2 && BR2_i386
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default "i686" if BR2_x86_corei7 && BR2_i386
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default "i686" if BR2_x86_atom && BR2_i386
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default "i686" if BR2_x86_opteron && BR2_i386
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default "i686" if BR2_x86_opteron_sse3 && BR2_i386
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default "i686" if BR2_x86_barcelona && BR2_i386
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default "i686" if BR2_x86_jaguar && BR2_i386
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default "i686" if BR2_x86_k6
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default "i686" if BR2_x86_k6_2
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default "i686" if BR2_x86_athlon
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default "i686" if BR2_x86_athlon_4
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default "x86_64" if BR2_x86_64
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config BR2_ENDIAN
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default "LITTLE"
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config BR2_ARCH_HAS_ATOMICS
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default y if !BR2_x86_i386
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config BR2_GCC_TARGET_ARCH
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default "i386" if BR2_x86_i386
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default "i486" if BR2_x86_i486
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default "i586" if BR2_x86_i586
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default "pentium-mmx" if BR2_x86_pentium_mmx
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default "i686" if BR2_x86_i686
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default "pentiumpro" if BR2_x86_pentiumpro
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default "pentium-m" if BR2_x86_pentium_m
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default "pentium2" if BR2_x86_pentium2
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default "pentium3" if BR2_x86_pentium3
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default "pentium4" if BR2_x86_pentium4
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default "prescott" if BR2_x86_prescott
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default "nocona" if BR2_x86_nocona
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default "core2" if BR2_x86_core2
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default "corei7" if BR2_x86_corei7
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default "atom" if BR2_x86_atom
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default "k8" if BR2_x86_opteron
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default "k8-sse3" if BR2_x86_opteron_sse3
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default "barcelona" if BR2_x86_barcelona
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default "btver2" if BR2_x86_jaguar
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default "k6" if BR2_x86_k6
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default "k6-2" if BR2_x86_k6_2
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default "athlon" if BR2_x86_athlon
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default "athlon-4" if BR2_x86_athlon_4
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default "winchip-c6" if BR2_x86_winchip_c6
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default "winchip2" if BR2_x86_winchip2
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default "c3" if BR2_x86_c3
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default "c3-2" if BR2_x86_c32
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default "geode" if BR2_x86_geode
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