2c6e667caa
This is a set of patch to add support for warpboard (Freescale board based on imx6sl) The patch contains : - defconfig for warpboard - linux patches from Fabio Estevam to fix device tree due to last change on warpboard schematics (rev 1.12) and to fix kernel imx_v6_v7 defconfig which use incorrect hci protocol - specific firmware file for warpboard bluetooth nvram : brcmfmac4330-sdio.txt Origin of nvram config file for wifi : https://github.com/Freescale/meta-fsl-arm-extra [Thomas: misc rewording/improvements in the README file.] Signed-off-by: Arthur LAMBERT <arthur@dreem.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
104 lines
2.6 KiB
Diff
104 lines
2.6 KiB
Diff
From: Fabio Estevam <fabio.estevam@freescale.com>
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Date: Fri, 29 May 2015 16:19:39 -0300
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Subject: [PATCH] ARM: dts: imx6sl-warp: Add changes for rev1.12
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Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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---
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arch/arm/boot/dts/imx6sl-warp.dts | 32 +++++++++++++++++++-------------
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1 file changed, 19 insertions(+), 13 deletions(-)
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diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts
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index 0da906b..bdfa82b 100644
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--- a/arch/arm/boot/dts/imx6sl-warp.dts
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+++ b/arch/arm/boot/dts/imx6sl-warp.dts
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@@ -61,7 +61,9 @@
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usdhc3_pwrseq: usdhc3_pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
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+ <&gpio4 7 GPIO_ACTIVE_LOW>, /* WL_HOSTWAKE */
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<&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */
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+ <&gpio3 27 GPIO_ACTIVE_LOW>, /* BT_HOSTWAKE */
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<&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */
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<&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */
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};
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@@ -73,16 +75,16 @@
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status = "okay";
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};
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-&uart2 {
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+&uart3 {
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pinctrl-names = "default";
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- pinctrl-0 = <&pinctrl_uart2>;
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- fsl,uart-has-rtscts;
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+ pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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-&uart3 {
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+&uart5 {
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pinctrl-names = "default";
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- pinctrl-0 = <&pinctrl_uart3>;
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+ pinctrl-0 = <&pinctrl_uart5>;
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+ fsl,uart-has-rtscts;
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status = "okay";
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};
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@@ -130,14 +132,6 @@
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>;
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};
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- pinctrl_uart2: uart2grp {
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- fsl,pins = <
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- MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x41b0b1
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- MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x41b0b1
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- MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x4130B1
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- MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x4130B1
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- >;
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- };
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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@@ -146,6 +140,15 @@
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>;
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};
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+ pinctrl_uart5: uart5grp {
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+ fsl,pins = <
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+ MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1
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+ MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1
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+ MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1
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+ MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1
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+ >;
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+ };
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+
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059
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@@ -158,6 +161,7 @@
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MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059
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MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059
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MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059
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+ MX6SL_PAD_SD2_RST__SD2_RESET 0x417059
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>;
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};
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@@ -173,6 +177,7 @@
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MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9
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MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9
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MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9
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+ MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9
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>;
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};
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@@ -188,6 +193,7 @@
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MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9
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MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9
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MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9
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+ MX6SL_PAD_SD2_RST__SD2_RESET 0x4170f9
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>;
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};
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--
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1.9.1
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