6f9431c3ad
This patch adds support for Xilinx Kria KD240 starter kit. KD240 features can be found here: https://www.xilinx.com/products/som/kria/kd240-drives-starter-kit.html While the Kria SOM is based on a ZynqMP SoC, there are some key boot config differences from the other ZynqMP evaluation boards. 1. There are no boot switches on Kria SOMs. The boot mode is thus hard configured for QSPI flash. A pre-programmed boot.bin comes with every Starter Kit. U-Boot can then find the Linux kernel and file system on the SD card. Optional instructions for updating the boot.bin in the QSPI flash can be found in the readme.txt file and the link below. https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM 2. Kria SOMs use UART1 for the console instead of UART0. For this reason, Kria Starter Kits will use a separate extlinux.conf file from other ZynqMP evaluation boards. 3. The KD240 has a USB to SD card bridge, so the Linux kernel and file system are found on /dev/sda1 and /dev/sda2. 4. The following patches have been submitted upstream to u-boot. Without these patches, the usb, sd card and ethernet peripherals do not work correctly. https://patchwork.ozlabs.org/project/uboot/patch/20231213134007.2818069-1-neal.frager@amd.com/ https://patchwork.ozlabs.org/project/uboot/patch/20231213134052.2818879-1-neal.frager@amd.com/ Signed-off-by: Neal Frager <neal.frager@amd.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> [Peter: add upstream tag, drop patch numbering from patches] Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
80 lines
2.2 KiB
Diff
80 lines
2.2 KiB
Diff
From bf35bdac2adfa7c65c2992d8dedcc24585561732 Mon Sep 17 00:00:00 2001
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From: Neal Frager <neal.frager@amd.com>
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Date: Wed, 13 Dec 2023 13:11:42 +0000
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Subject: [PATCH] arm64: zynqmp: Add output-enable pins to SOMs
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Now that the zynqmp pinctrl driver supports the tri-state registers, make
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sure that the pins requiring output-enable are configured appropriately for
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SOMs.
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Without it, all tristate setting for MIOs, which are not related to SOM
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itself, are using default configuration which is not correct setting.
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It means SDs, USBs, ethernet, etc. are not working properly.
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In past it was fixed through calling tristate configuration via bootcmd:
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usb_init=mw 0xFF180208 2020
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kv260_gem3=mw 0xFF18020C 0xFC0 && gpio toggle gpio@ff0a000038 && \
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gpio toggle gpio@ff0a000038
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Signed-off-by: Neal Frager <neal.frager@amd.com>
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Upstream: https://patchwork.ozlabs.org/project/uboot/patch/20231213134052.2818879-1-neal.frager@amd.com/
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---
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arch/arm/dts/zynqmp-sck-kd-g-revA.dts | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dts b/arch/arm/dts/zynqmp-sck-kd-g-revA.dts
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index 56f3128528..12865392a3 100644
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--- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dts
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+++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dts
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@@ -175,6 +175,7 @@
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conf-tx {
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pins = "MIO36";
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bias-disable;
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+ output-enable;
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};
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mux {
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@@ -226,6 +227,7 @@
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conf-bootstrap {
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pins = "MIO44", "MIO49";
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bias-disable;
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+ output-enable;
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low-power-disable;
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};
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@@ -233,6 +235,7 @@
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pins = "MIO38", "MIO39", "MIO40",
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"MIO41", "MIO42", "MIO43";
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bias-disable;
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+ output-enable;
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low-power-enable;
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};
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@@ -241,6 +244,7 @@
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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+ output-enable;
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};
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mux-mdio {
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@@ -271,6 +275,7 @@
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pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
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"MIO60", "MIO61", "MIO62", "MIO63";
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bias-disable;
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+ output-enable;
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drive-strength = <4>;
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slew-rate = <SLEW_RATE_SLOW>;
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};
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@@ -298,6 +303,7 @@
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pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
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"MIO72", "MIO73", "MIO74", "MIO75";
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bias-disable;
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+ output-enable;
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drive-strength = <4>;
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slew-rate = <SLEW_RATE_SLOW>;
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};
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--
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2.25.1
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