Thomas De Schampheleire 18b8d360bb arch/mips: add (Marvell) Octeon III processor ... The compiler recognizes a specific 'march' value for Octeon III processors, so create a 'Target Architecture Variant' entry for it in the target menu. Note: support for '-march=octeon3' was added in gcc 5.x. However, the official compiler provided by Marvell (Cavium Networks) uses gcc 4.7.x (and supports -march=octeon3 via their own modifications). For this reason, no line 'select BR2_ARCH_NEEDS_GCC_AT_LEAST_5' is added. Signed-off-by: Thomas De Schampheleire <thomas.de_schampheleire@nokia.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>		2019-02-04 17:30:18 +01:00
..
arch.mk	arch: drop BR2_GCC_TARGET_CPU_REVISION option	2018-10-01 14:52:32 +02:00
arch.mk.riscv	arch: add support for RISC-V 32-bit (riscv32) architecture	2019-01-06 14:09:31 +01:00
arch.mk.xtensa	arc/xtensa: store the Xtensa overlay in the per-package DL_DIR	2018-04-02 15:59:30 +02:00
Config.in	arch: drop BR2_GCC_TARGET_CPU_REVISION option	2018-10-01 14:52:32 +02:00
Config.in.arc
Config.in.arm	arch/arm: add an armv8.3a core	2018-12-30 16:10:04 +01:00
Config.in.csky
Config.in.m68k
Config.in.microblaze
Config.in.mips	arch/mips: add (Marvell) Octeon III processor	2019-02-04 17:30:18 +01:00
Config.in.nios2
Config.in.or1k
Config.in.powerpc
Config.in.riscv	arch: add support for RISC-V 32-bit (riscv32) architecture	2019-01-06 14:09:31 +01:00
Config.in.sh
Config.in.sparc
Config.in.x86
Config.in.xtensa