ea033cecf9
Spike, the RISC-V ISA Simulator, implements a functional model of one or more RISC-V harts. The host package provides an alternative solution to qemu. https://github.com/riscv-software-src/riscv-isa-sim Signed-off-by: Julien Olivain <ju.o@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
35 lines
869 B
Diff
35 lines
869 B
Diff
From 980d5143089bf32ef8a6dfdf1bb9e9fe92fa7bf5 Mon Sep 17 00:00:00 2001
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From: Julien Olivain <ju.o@free.fr>
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Date: Sun, 9 Jan 2022 13:38:48 +0100
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Subject: [PATCH] riscv: disable precompiled headers
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While precompiling header, some toolchains fail with the message:
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/path/to/toolchain/bin/ld: /path/to/sysroot/usr/lib/Scrt1.o: in function `_start':
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(.text+0x54): undefined reference to `main'
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The patch totally disable precompiled headers.
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Signed-off-by: Julien Olivain <ju.o@free.fr>
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---
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riscv/riscv.mk.in | 3 ---
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1 file changed, 3 deletions(-)
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diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
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index 2347ce6..4f56eaf 100644
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--- a/riscv/riscv.mk.in
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+++ b/riscv/riscv.mk.in
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@@ -35,9 +35,6 @@ riscv_hdrs = \
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riscv_install_hdrs = mmio_plugin.h
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-riscv_precompiled_hdrs = \
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- insn_template.h \
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-
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riscv_srcs = \
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processor.cc \
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execute.cc \
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--
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2.34.1
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