7f00b62917
The largefile patch is no longer necessary, it has been merged upstream. However, in order to make the build work properly with Thumb2 toolchains (such as Linaro toolchains), an additional fix is needed. This fix is already upstream and will be part of upcoming Xenomai releases. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
158 lines
5.1 KiB
Diff
158 lines
5.1 KiB
Diff
From ad3714e925f5c6b4ae0e0d31c4bab7f8c5e659db Mon Sep 17 00:00:00 2001
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From: Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>
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Date: Fri, 10 Aug 2012 21:55:41 +0200
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Subject: [PATCH] hal/arm: fix compilation for thumb
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---
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include/asm-arm/atomic.h | 3 ++
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ksrc/arch/arm/switch.S | 84 +++++++++++++++++++++++++++------------------
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2 files changed, 53 insertions(+), 34 deletions(-)
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diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h
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index 5d55ae8..ae96847 100644
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--- a/include/asm-arm/atomic.h
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+++ b/include/asm-arm/atomic.h
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@@ -183,6 +183,9 @@ xnarch_atomic_cmpxchg(xnarch_atomic_t *ptr,
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"ldrex %1, [%3]\n"
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"mov %0, #0\n"
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"teq %1, %4\n"
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+#ifdef __thumb__
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+ "it eq\n"
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+#endif
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"strexeq %0, %5, [%3]\n"
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: "=&r" (res), "=&r" (curval), "+Qo" (ptr->counter)
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: "r" (&ptr->counter), "Ir" (oldval), "r" (newval)
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diff --git a/ksrc/arch/arm/switch.S b/ksrc/arch/arm/switch.S
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index 83f4746..95c355f 100644
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--- a/ksrc/arch/arm/switch.S
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+++ b/ksrc/arch/arm/switch.S
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@@ -37,6 +37,11 @@
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.endm
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#endif
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+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31)
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+#define ARM(x...) x
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+#define THUMB(x...)
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+#endif
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+
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#if LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 37)
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#ifdef CONFIG_MMU
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#define USE_DOMAINS
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@@ -83,18 +88,19 @@
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* r0 = pointer to union vfp_state, r1 = fpexc
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*/
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ENTRY(rthal_vfp_save)
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- VFPFSTMIA r0, r2 @ save the working registers
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- VFPFMRX r2, FPSCR @ current status
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- tst r1, #FPEXC_EX @ is there additional state to save?
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- beq 1f
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- VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set)
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- tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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- beq 1f
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- VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present)
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+ VFPFSTMIA r0, r2 @ save the working registers
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+ VFPFMRX r2, FPSCR @ current status
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+ tst r1, #FPEXC_EX @ is there additional state to save?
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+ beq 1f
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+ VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set)
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+ tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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+ beq 1f
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+ VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present)
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1:
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- stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
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- mov pc, lr
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-
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+ stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
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+ mov pc, lr
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+ENDPROC(rthal_vfp_save)
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+
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/* Copied from no_old_VFP_process in arch/arm/vfp/vfphw.S
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* r0 = pointer to union vfp_state
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* r1 = current cpu
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@@ -102,20 +108,21 @@ ENTRY(rthal_vfp_save)
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ENTRY(rthal_vfp_load)
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0) \
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|| defined(CONFIG_VFP_3_2_BACKPORT)) && defined(CONFIG_SMP)
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- str r1, [r0, #VFP_CPU]
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+ str r1, [r0, #VFP_CPU]
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#endif
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- VFPFLDMIA r0, r2 @ reload the working registers while
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+ VFPFLDMIA r0, r2 @ reload the working registers while
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@ FPEXC is in a safe state
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- ldmia r0, {r1, r2, r3, r12} @ load FPEXC, FPSCR, FPINST, FPINST2
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- tst r1, #FPEXC_EX @ is there additional state to restore?
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- beq 1f
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- VFPFMXR FPINST, r3 @ restore FPINST (only if FPEXC.EX is set)
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- tst r1, #FPEXC_FP2V @ is there an FPINST2 to write?
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- beq 1f
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- VFPFMXR FPINST2, r12 @ FPINST2 if needed (and present)
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+ ldmia r0, {r1, r2, r3, r12} @ load FPEXC, FPSCR, FPINST, FPINST2
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+ tst r1, #FPEXC_EX @ is there additional state to restore?
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+ beq 1f
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+ VFPFMXR FPINST, r3 @ restore FPINST (only if FPEXC.EX is set)
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+ tst r1, #FPEXC_FP2V @ is there an FPINST2 to write?
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+ beq 1f
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+ VFPFMXR FPINST2, r12 @ FPINST2 if needed (and present)
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1:
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- VFPFMXR FPSCR, r2 @ restore status
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- mov pc, lr
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+ VFPFMXR FPSCR, r2 @ restore status
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+ mov pc, lr
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+ENDPROC(rthal_vfp_load)
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#endif
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/*
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@@ -144,28 +151,37 @@ ENTRY(rthal_vfp_load)
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* r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
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*/
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ENTRY(rthal_thread_switch)
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- add ip, r1, #TI_CPU_SAVE
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- ldr r3, [r2, #TI_TP_VALUE]
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- stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
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+ add ip, r1, #TI_CPU_SAVE
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+ ldr r3, [r2, #TI_TP_VALUE]
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+ ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
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+ THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
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+ THUMB( str sp, [ip], #4 )
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+ THUMB( str lr, [ip], #4 )
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#ifdef USE_DOMAINS
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- ldr r6, [r2, #TI_CPU_DOMAIN]
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+ ldr r6, [r2, #TI_CPU_DOMAIN]
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#endif
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- clear_exclusive_monitor
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- set_tls r3, r4, r5
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+ clear_exclusive_monitor
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+ set_tls r3, r4, r5
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#ifdef USE_DOMAINS
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- mcr p15, 0, r6, c3, c0, 0 @ Set domain register
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+ mcr p15, 0, r6, c3, c0, 0 @ Set domain register
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#endif
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- fpu_switch r4
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- add r4, r2, #TI_CPU_SAVE
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- ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
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+ fpu_switch r4
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+ ARM( add r4, r2, #TI_CPU_SAVE )
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+ ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
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+ THUMB( add ip, r2, #TI_CPU_SAVE )
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+ THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
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+ THUMB( ldr sp, [ip], #4 )
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+ THUMB( ldr pc, [ip] )
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+ENDPROC(rthal_thread_switch)
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/*
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* r4 = xnarch_thread_trampoline
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* r5 = xnarchtcb_t *
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*/
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ENTRY(rthal_thread_trampoline)
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- mov r0, r5
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- mov pc, r4
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+ mov r0, r5
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+ mov pc, r4
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+ENDPROC(rthal_thread_trampoline)
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// vim: ts=4 et sw=4 sts=4
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--
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1.7.2.5
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