4353c71646
Backported from upstream GDB geb79b23, with ChangeLogs stripped so the
patch applies properly on Buildroot.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=eb79b23
Fixes the following issue:
# gdbserver /dev/hvc1 inadyn -n -l debug
Process inadyn created; pid = 675
Remote debugging using /dev/hvc1
../../gdbserver/regcache.cc:257: A problem internal to GDBserver has been detected.
Unknown register tag_ctl requested
Signed-off-by: Joachim Wiberg <troglobit@gmail.com>
[yann.morin.1998@free.fr: add SoB in patch, provided live on IRC]
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
321 lines
10 KiB
Diff
321 lines
10 KiB
Diff
From eb79b2318066cafb75ffdce310e3bbd44f7c79e3 Mon Sep 17 00:00:00 2001
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From: Luis Machado <luis.machado@linaro.org>
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Date: Fri, 29 Oct 2021 14:54:36 -0300
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Subject: [PATCH] [AArch64] Make gdbserver register set selection dynamic
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The current register set selection mechanism for AArch64 is static, based
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on a pre-populated array of register sets.
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This means that we might potentially probe register sets that are not
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available. This is OK if the kernel errors out during ptrace, but probing the
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tag_ctl register, for example, does not result in a ptrace error if the kernel
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supports the tagged address ABI but not MTE (PR 28355).
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Making the register set selection dynamic, based on feature checks, solves
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this and simplifies the code a bit. It allows us to list all of the register
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sets only once, and pick and choose based on HWCAP/HWCAP2 or other properties.
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gdb/ChangeLog:
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2021-11-03 Luis Machado <luis.machado@linaro.org>
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PR gdb/28355
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* arch/aarch64.h (struct aarch64_features): New struct.
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gdbserver/ChangeLog:
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2021-11-03 Luis Machado <luis.machado@linaro.org>
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PR gdb/28355
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* linux-aarch64-low.cc (is_sve_tdesc): Remove.
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(aarch64_target::low_arch_setup): Rework to adjust the register sets.
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(aarch64_regsets): Update to list all register sets.
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(aarch64_regsets_info, regs_info_aarch64): Replace NULL with nullptr.
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(aarch64_sve_regsets, aarch64_sve_regsets_info)
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(regs_info_aarch64_sve): Remove.
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(aarch64_adjust_register_sets): New.
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(aarch64_target::get_regs_info): Remove references to removed structs.
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(initialize_low_arch): Likewise.
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Backported from: eb79b2318066cafb75ffdce310e3bbd44f7c79e3
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Signed-off-by: Joachim Wiberg <troglobit@gmail.com>
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---
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gdb/arch/aarch64.h | 9 ++
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gdbserver/linux-aarch64-low.cc | 186 ++++++++++++++++++---------------
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4 files changed, 130 insertions(+), 85 deletions(-)
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diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h
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index 0eb702c5b5e..95edb664b55 100644
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--- a/gdb/arch/aarch64.h
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+++ b/gdb/arch/aarch64.h
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@@ -22,6 +22,15 @@
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#include "gdbsupport/tdesc.h"
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+/* Holds information on what architectural features are available. This is
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+ used to select register sets. */
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+struct aarch64_features
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+{
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+ bool sve = false;
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+ bool pauth = false;
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+ bool mte = false;
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+};
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+
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/* Create the aarch64 target description. A non zero VQ value indicates both
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the presence of SVE and the Vector Quotient - the number of 128bit chunks in
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an SVE Z register. HAS_PAUTH_P indicates the presence of the PAUTH
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diff --git a/gdbserver/linux-aarch64-low.cc b/gdbserver/linux-aarch64-low.cc
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index daccfef746e..9a8cb4169a7 100644
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--- a/gdbserver/linux-aarch64-low.cc
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+++ b/gdbserver/linux-aarch64-low.cc
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@@ -196,16 +196,6 @@ is_64bit_tdesc (void)
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return register_size (regcache->tdesc, 0) == 8;
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}
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-/* Return true if the regcache contains the number of SVE registers. */
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-
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-static bool
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-is_sve_tdesc (void)
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-{
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- struct regcache *regcache = get_thread_regcache (current_thread, 0);
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-
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- return tdesc_contains_feature (regcache->tdesc, "org.gnu.gdb.aarch64.sve");
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-}
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-
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static void
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aarch64_fill_gregset (struct regcache *regcache, void *buf)
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{
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@@ -680,40 +670,6 @@ aarch64_target::low_new_fork (process_info *parent,
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*child->priv->arch_private = *parent->priv->arch_private;
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}
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-/* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */
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-#define AARCH64_HWCAP_PACA (1 << 30)
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-
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-/* Implementation of linux target ops method "low_arch_setup". */
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-
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-void
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-aarch64_target::low_arch_setup ()
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-{
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- unsigned int machine;
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- int is_elf64;
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- int tid;
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-
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- tid = lwpid_of (current_thread);
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-
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- is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
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-
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- if (is_elf64)
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- {
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- uint64_t vq = aarch64_sve_get_vq (tid);
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- unsigned long hwcap = linux_get_hwcap (8);
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- unsigned long hwcap2 = linux_get_hwcap2 (8);
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- bool pauth_p = hwcap & AARCH64_HWCAP_PACA;
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- /* MTE is AArch64-only. */
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- bool mte_p = hwcap2 & HWCAP2_MTE;
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-
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- current_process ()->tdesc
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- = aarch64_linux_read_description (vq, pauth_p, mte_p);
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- }
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- else
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- current_process ()->tdesc = aarch32_linux_read_description ();
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-
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- aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread));
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-}
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-
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/* Wrapper for aarch64_sve_regs_copy_to_reg_buf. */
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static void
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@@ -730,21 +686,36 @@ aarch64_sve_regs_copy_from_regcache (struct regcache *regcache, void *buf)
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return aarch64_sve_regs_copy_from_reg_buf (regcache, buf);
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}
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+/* Array containing all the possible register sets for AArch64/Linux. During
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+ architecture setup, these will be checked against the HWCAP/HWCAP2 bits for
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+ validity and enabled/disabled accordingly.
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+
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+ Their sizes are set to 0 here, but they will be adjusted later depending
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+ on whether each register set is available or not. */
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static struct regset_info aarch64_regsets[] =
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{
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+ /* GPR registers. */
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{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
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- sizeof (struct user_pt_regs), GENERAL_REGS,
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+ 0, GENERAL_REGS,
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aarch64_fill_gregset, aarch64_store_gregset },
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+ /* Floating Point (FPU) registers. */
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{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET,
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- sizeof (struct user_fpsimd_state), FP_REGS,
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+ 0, FP_REGS,
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aarch64_fill_fpregset, aarch64_store_fpregset
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},
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+ /* Scalable Vector Extension (SVE) registers. */
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+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_SVE,
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+ 0, EXTENDED_REGS,
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+ aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache
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+ },
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+ /* PAC registers. */
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{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK,
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- AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS,
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- NULL, aarch64_store_pauthregset },
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+ 0, OPTIONAL_REGS,
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+ nullptr, aarch64_store_pauthregset },
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+ /* Tagged address control / MTE registers. */
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{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL,
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- AARCH64_LINUX_SIZEOF_MTE, OPTIONAL_REGS, aarch64_fill_mteregset,
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- aarch64_store_mteregset },
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+ 0, OPTIONAL_REGS,
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+ aarch64_fill_mteregset, aarch64_store_mteregset },
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NULL_REGSET
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};
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@@ -752,47 +723,95 @@ static struct regsets_info aarch64_regsets_info =
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{
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aarch64_regsets, /* regsets */
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0, /* num_regsets */
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- NULL, /* disabled_regsets */
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+ nullptr, /* disabled_regsets */
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};
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static struct regs_info regs_info_aarch64 =
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{
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- NULL, /* regset_bitmap */
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- NULL, /* usrregs */
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+ nullptr, /* regset_bitmap */
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+ nullptr, /* usrregs */
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&aarch64_regsets_info,
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};
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-static struct regset_info aarch64_sve_regsets[] =
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+/* Given FEATURES, adjust the available register sets by setting their
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+ sizes. A size of 0 means the register set is disabled and won't be
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+ used. */
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+
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+static void
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+aarch64_adjust_register_sets (const struct aarch64_features &features)
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{
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- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
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- sizeof (struct user_pt_regs), GENERAL_REGS,
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- aarch64_fill_gregset, aarch64_store_gregset },
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- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_SVE,
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- SVE_PT_SIZE (AARCH64_MAX_SVE_VQ, SVE_PT_REGS_SVE), EXTENDED_REGS,
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- aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache
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- },
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- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK,
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- AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS,
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- NULL, aarch64_store_pauthregset },
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- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL,
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- AARCH64_LINUX_SIZEOF_MTE, OPTIONAL_REGS, aarch64_fill_mteregset,
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- aarch64_store_mteregset },
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- NULL_REGSET
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-};
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+ struct regset_info *regset;
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-static struct regsets_info aarch64_sve_regsets_info =
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- {
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- aarch64_sve_regsets, /* regsets. */
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- 0, /* num_regsets. */
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- NULL, /* disabled_regsets. */
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- };
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+ for (regset = aarch64_regsets; regset->size >= 0; regset++)
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+ {
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+ switch (regset->nt_type)
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+ {
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+ case NT_PRSTATUS:
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+ /* General purpose registers are always present. */
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+ regset->size = sizeof (struct user_pt_regs);
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+ break;
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+ case NT_FPREGSET:
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+ /* This is unavailable when SVE is present. */
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+ if (!features.sve)
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+ regset->size = sizeof (struct user_fpsimd_state);
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+ break;
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+ case NT_ARM_SVE:
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+ if (features.sve)
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+ regset->size = SVE_PT_SIZE (AARCH64_MAX_SVE_VQ, SVE_PT_REGS_SVE);
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+ break;
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+ case NT_ARM_PAC_MASK:
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+ if (features.pauth)
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+ regset->size = AARCH64_PAUTH_REGS_SIZE;
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+ break;
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+ case NT_ARM_TAGGED_ADDR_CTRL:
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+ if (features.mte)
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+ regset->size = AARCH64_LINUX_SIZEOF_MTE;
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+ break;
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+ default:
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+ gdb_assert_not_reached ("Unknown register set found.");
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+ }
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+ }
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+}
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-static struct regs_info regs_info_aarch64_sve =
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- {
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- NULL, /* regset_bitmap. */
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- NULL, /* usrregs. */
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- &aarch64_sve_regsets_info,
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- };
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+/* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */
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+#define AARCH64_HWCAP_PACA (1 << 30)
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+
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+/* Implementation of linux target ops method "low_arch_setup". */
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+
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+void
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+aarch64_target::low_arch_setup ()
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+{
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+ unsigned int machine;
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+ int is_elf64;
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+ int tid;
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+
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+ tid = lwpid_of (current_thread);
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+
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+ is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
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+
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+ if (is_elf64)
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+ {
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+ struct aarch64_features features;
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+
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+ uint64_t vq = aarch64_sve_get_vq (tid);
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+ features.sve = (vq > 0);
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+ /* A-profile PAC is 64-bit only. */
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+ features.pauth = linux_get_hwcap (8) & AARCH64_HWCAP_PACA;
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+ /* A-profile MTE is 64-bit only. */
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+ features.mte = linux_get_hwcap2 (8) & HWCAP2_MTE;
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+
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+ current_process ()->tdesc
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+ = aarch64_linux_read_description (vq, features.pauth, features.mte);
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+
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+ /* Adjust the register sets we should use for this particular set of
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+ features. */
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+ aarch64_adjust_register_sets (features);
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+ }
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+ else
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+ current_process ()->tdesc = aarch32_linux_read_description ();
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+
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+ aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread));
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+}
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/* Implementation of linux target ops method "get_regs_info". */
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@@ -802,9 +821,7 @@ aarch64_target::get_regs_info ()
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if (!is_64bit_tdesc ())
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return ®s_info_aarch32;
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- if (is_sve_tdesc ())
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- return ®s_info_aarch64_sve;
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-
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+ /* AArch64 64-bit registers. */
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return ®s_info_aarch64;
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}
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@@ -3294,5 +3311,4 @@ initialize_low_arch (void)
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initialize_low_arch_aarch32 ();
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initialize_regsets_info (&aarch64_regsets_info);
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- initialize_regsets_info (&aarch64_sve_regsets_info);
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}
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--
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2.27.0
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