742f37de8d
Bump most QEMU defconfigs (every one that was previously on 5.4.y)
to latest longterm kernel 5.10.7.
Please note the following exceptions/modifications:
- board/qemu/qemu_s390x_defconfig: ignored (already up to date)
- board/qemu/sh4*-r2d:
- Remove the remaining kernel patch [1] provided by Alan Modra
fixing rodata alignment, carried here by Romain Naour [2] to
fix an issue preventing kernel from booting with binutils 2.23.
Patch is present in upstream Linux now.
- Fix compile-time error regarding 64-bit time data structures
from kernel headers when building with uclibc. Previous fix [3]
existed upstream; but see details below.
- board/qemu/ppc-mpc8544ds: Updated kernel patch
- board/qemu/arm-versatile: Updated kernel patch
- board/qemu/mips*r6*: Updated kernel patch
Tested on all configs/qemu* configurations. [4]
[1] https://www.sourceware.org/ml/binutils/2019-12/msg00112.html
[2] https://git.busybox.net/buildroot/commit/?id=a2331c8a61bdd71c47492efc818fb0458a349219
[3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=fc94cf2092c7c1267fa2deb8388d624f50eba808
[4] https://gitlab.com/clumsyape/buildroot/-/pipelines/244024195
Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@gmail.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
150 lines
4.6 KiB
Diff
150 lines
4.6 KiB
Diff
From b9af6f34e43bf5264d75933f2080f16b8741048d Mon Sep 17 00:00:00 2001
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From: Romain Naour <romain.naour@gmail.com>
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Date: Sat, 25 Jul 2020 11:46:01 +0200
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Subject: [PATCH] mips: Do not include hi and lo in clobber list for R6
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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From [1]
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"GCC 10 (PR 91233) won't silently allow registers that are not architecturally
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available to be present in the clobber list anymore, resulting in build failure
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for mips*r6 targets in form of:
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...
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.../sysdep.h:146:2: error: the register ‘lo’ cannot be clobbered in ‘asm’ for the current target
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146 | __asm__ volatile ( \
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| ^~~~~~~
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This is because base R6 ISA doesn't define hi and lo registers w/o DSP extension.
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This patch provides the alternative clobber list for r6 targets that won't include
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those registers."
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Since kernel 5.4 and mips support for generic vDSO [2], the kernel fail to build
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for mips r6 cpus with gcc 10 for the same reason as glibc.
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[1] https://sourceware.org/git/?p=glibc.git;a=commit;h=020b2a97bb15f807c0482f0faee2184ed05bcad8
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[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=24640f233b466051ad3a5d2786d2951e43026c9d
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Signed-off-by: Romain Naour <romain.naour@gmail.com>
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---
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arch/mips/include/asm/vdso/gettimeofday.h | 45 +++++++++++++++++++++++
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1 file changed, 45 insertions(+)
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diff --git a/arch/mips/include/asm/vdso/gettimeofday.h b/arch/mips/include/asm/vdso/gettimeofday.h
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index 2203e2d0ae2a..e28096faecf6 100644
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--- a/arch/mips/include/asm/vdso/gettimeofday.h
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+++ b/arch/mips/include/asm/vdso/gettimeofday.h
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@@ -30,12 +30,21 @@ static __always_inline long gettimeofday_fallback(
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register long nr asm("v0") = __NR_gettimeofday;
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register long error asm("a3");
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+#if MIPS_ISA_REV >= 6
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+ asm volatile(
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+ " syscall\n"
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+ : "=r" (ret), "=r" (error)
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+ : "r" (tv), "r" (tz), "r" (nr)
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+ : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
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+ "$14", "$15", "$24", "$25", "memory");
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+#else
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asm volatile(
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" syscall\n"
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: "=r" (ret), "=r" (error)
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: "r" (tv), "r" (tz), "r" (nr)
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: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
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"$14", "$15", "$24", "$25", "hi", "lo", "memory");
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+#endif
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return error ? -ret : ret;
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}
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@@ -54,12 +63,21 @@ static __always_inline long clock_gettime_fallback(
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#endif
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register long error asm("a3");
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+#if MIPS_ISA_REV >= 6
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+ asm volatile(
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+ " syscall\n"
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+ : "=r" (ret), "=r" (error)
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+ : "r" (clkid), "r" (ts), "r" (nr)
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+ : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
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+ "$14", "$15", "$24", "$25", "memory");
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+#else
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asm volatile(
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" syscall\n"
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: "=r" (ret), "=r" (error)
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: "r" (clkid), "r" (ts), "r" (nr)
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: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
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"$14", "$15", "$24", "$25", "hi", "lo", "memory");
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+#endif
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return error ? -ret : ret;
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}
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@@ -78,12 +96,21 @@ static __always_inline int clock_getres_fallback(
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#endif
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register long error asm("a3");
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+#if MIPS_ISA_REV >= 6
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+ asm volatile(
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+ " syscall\n"
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+ : "=r" (ret), "=r" (error)
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+ : "r" (clkid), "r" (ts), "r" (nr)
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+ : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
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+ "$14", "$15", "$24", "$25", "memory");
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+#else
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asm volatile(
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" syscall\n"
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: "=r" (ret), "=r" (error)
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: "r" (clkid), "r" (ts), "r" (nr)
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: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
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"$14", "$15", "$24", "$25", "hi", "lo", "memory");
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+#endif
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return error ? -ret : ret;
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}
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@@ -100,12 +127,21 @@ static __always_inline long clock_gettime32_fallback(
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register long nr asm("v0") = __NR_clock_gettime;
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register long error asm("a3");
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+#if MIPS_ISA_REV >= 6
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+ asm volatile(
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+ " syscall\n"
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+ : "=r" (ret), "=r" (error)
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+ : "r" (clkid), "r" (ts), "r" (nr)
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+ : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
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+ "$14", "$15", "$24", "$25", "memory");
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+#else
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asm volatile(
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" syscall\n"
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: "=r" (ret), "=r" (error)
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: "r" (clkid), "r" (ts), "r" (nr)
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: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
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"$14", "$15", "$24", "$25", "hi", "lo", "memory");
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+#endif
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return error ? -ret : ret;
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}
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@@ -120,12 +156,21 @@ static __always_inline int clock_getres32_fallback(
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register long nr asm("v0") = __NR_clock_getres;
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register long error asm("a3");
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+#if MIPS_ISA_REV >= 6
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+ asm volatile(
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+ " syscall\n"
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+ : "=r" (ret), "=r" (error)
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+ : "r" (clkid), "r" (ts), "r" (nr)
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+ : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
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+ "$14", "$15", "$24", "$25", "memory");
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+#else
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asm volatile(
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" syscall\n"
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: "=r" (ret), "=r" (error)
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: "r" (clkid), "r" (ts), "r" (nr)
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: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
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"$14", "$15", "$24", "$25", "hi", "lo", "memory");
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+#endif
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return error ? -ret : ret;
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}
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--
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2.17.1
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