436 lines
13 KiB
C
436 lines
13 KiB
C
/*
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* (C) Copyright 2006
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* M. Amine SAYA ATMEL Rousset, France.
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*
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* Rick Bronson <rick@efn.org>
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*
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* Configuration settings for the AT91SAM9261EK board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_HOSTNAME at91sam9261ek
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/*
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* If we are developing, we might want to start armboot from ram
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* so we MUST NOT initialize critical regs like mem-timing ...
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*/
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/* ARM asynchronous clock */
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#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
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#define AT91C_MASTER_CLOCK 99300000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
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/* #define AT91C_MASTER_CLOCK 48000000 */
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/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
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#define AT91_SLOW_CLOCK 32768 /* slow clock */
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#define CFG_HZ 1000
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#define CONFIG_AT91 1
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#define CONFIG_ARM926EJS 1
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#define CONFIG_AT91SAM9261 1
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#define CONFIG_AT91SAM9261EK 1 /* on an AT91SAM9261EK Board */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* define this to include the functionality of boot.bin in u-boot */
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SKIP_RELOCATE_UBOOT
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#define BOARD_LATE_INIT 1 /* Don't know what this means for now */
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/*
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* Size of malloc() pool
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*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/*
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* Hardware drivers
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*/
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#define CONFIG_BOOTDELAY 3
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#undef CONFIG_ENV_OVERWRITE
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#define CONFIG_COMMANDS \
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((CONFIG_CMD_DFL | \
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CFG_CMD_NET | \
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CFG_CMD_PING | \
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CFG_CMD_ENV | \
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CFG_CMD_USB | \
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CFG_CMD_FLASH | \
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CFG_CMD_AUTOSCRIPT | \
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CFG_CMD_DHCP | \
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CFG_CMD_NAND | \
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CFG_CMD_FAT ) & \
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~(CFG_CMD_BDI | \
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CFG_CMD_IMLS | \
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CFG_CMD_IMI | \
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CFG_CMD_FPGA | \
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CFG_CMD_MISC | \
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CFG_CMD_LOADS))
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/* UART Configuration */
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
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#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
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/* Console Configuration */
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#define CFG_CONSOLE_IS_SERIAL
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#undef CFG_CONSOLE_IS_LCD
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#define CONFIG_AUTO_COMPLETE
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#define CFG_LONGHELP
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/* define one of these to choose the DBGU, USART0 or USART1 as console */
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#define CONFIG_DBGU 1
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#undef CONFIG_USART0
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#undef CONFIG_USART1
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#undef CONFIG_USART2
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#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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/* Ethernet Configuration */
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#define CONFIG_DRIVER_ETHER 1
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#define CONFIG_NET_RETRY_COUNT 5000
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#define CONFIG_TFTP_TIMEOUT 2500 /*250*/
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#define CONFIG_ETHINIT 1
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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#define CONFIG_DRIVER_DM9000 1
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#define CONFIG_AT91C_USE_RMII
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#define CONFIG_DM9000_BASE 0x30000000
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#define DM9000_IO CONFIG_DM9000_BASE
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#define DM9000_DATA (CONFIG_DM9000_BASE+4)
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#undef CONFIG_DM9000_USE_8BIT
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#define CONFIG_DM9000_USE_16BIT 1
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#undef CONFIG_DM9000_USE_32BIT
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#undef CONFIG_DM9000_DEBUG
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#ifdef CONFIG_DRIVER_DM9000
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/*
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* SMC Chip Select 2 Timings for DM9000 (davicom).
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* These timings were calculated for MASTER_CLOCK = 48000000
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* according to DM9000 timings. Refer to SMC user interface
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* in AT91SAM9261 datasheet to learn how to regenerate these
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* values in case MASTER_CLOCK changes.
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*/
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/*
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#define AT91C_DM9000_NWE_SETUP (1 << 0)
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#define AT91C_DM9000_NCS_WR_SETUP (0 << 8)
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#define AT91C_DM9000_NRD_SETUP (1 << 16)
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#define AT91C_DM9000_NCS_RD_SETUP (0 << 24)
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#define AT91C_DM9000_NWE_PULSE (2 << 0)
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#define AT91C_DM9000_NCS_WR_PULSE (4 << 8)
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#define AT91C_DM9000_NRD_PULSE (2 << 16)
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#define AT91C_DM9000_NCS_RD_PULSE (4 << 24)
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#define AT91C_DM9000_NWE_CYCLE (8 << 0)
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#define AT91C_DM9000_NRD_CYCLE (8 << 16)
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#define AT91C_DM9000_TDF (1 << 16)
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*/
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/*
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* SMC Chip Select 2 Timings for DM9000 (davicom).
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* These timings were calculated for MASTER_CLOCK = 100000000
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* according to DM9000 timings. Refer to SMC user interface
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* in AT91SAM9261 datasheet to learn how to regenerate these
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* values in case MASTER_CLOCK changes.
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*/
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#define AT91C_DM9000_NWE_SETUP (2 << 0)
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#define AT91C_DM9000_NCS_WR_SETUP (0 << 8)
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#define AT91C_DM9000_NRD_SETUP (2 << 16)
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#define AT91C_DM9000_NCS_RD_SETUP (0 << 24)
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#define AT91C_DM9000_NWE_PULSE (4 << 0)
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#define AT91C_DM9000_NCS_WR_PULSE (8 << 8)
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#define AT91C_DM9000_NRD_PULSE (4 << 16)
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#define AT91C_DM9000_NCS_RD_PULSE (8 << 24)
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#define AT91C_DM9000_NWE_CYCLE (16 << 0)
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#define AT91C_DM9000_NRD_CYCLE (16 << 16)
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#define AT91C_DM9000_TDF (1 << 16)
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#endif /* CONFIG_DRIVER_DM9000 */
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/* USB Configuration */
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#define CONFIG_USB_OHCI 1
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#define CONFIG_USB_STORAGE 1
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#define CONFIG_DOS_PARTITION 1
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#define LITTLEENDIAN 1
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#define PIO_ID AT91C_ID_PIOA
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#define PIO_LEDS AT91C_BASE_PIOA
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#define GREEN_LED AT91C_PIO_PA13
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#define GREEN_LED_ON PIO_CODR
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#define GREEN_LED_OFF PIO_SODR
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#define YELLOW_LED AT91C_PIO_PA23
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#define YELLOW_LED_ON PIO_CODR
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#define YELLOW_LED_OFF PIO_SODR
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/* RED LED is really "Green" */
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#define RED_LED AT91C_PIO_PA14
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#define RED_LED_ON PIO_CODR
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#define RED_LED_OFF PIO_SODR
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#define ALL_LEDS (GREEN_LED | YELLOW_LED | RED_LED)
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#define TIME_SLICE 500000
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/* LCD Configuration */
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#define CONFIG_LCD
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#define CONFIG_LCD_LOGO
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#undef LCD_TEST_PATTERN
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#define CONFIG_LCD_INFO
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#define CONFIG_LCD_INFO_BELOW_LOGO
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#undef CFG_INVERT_COLORS
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#define CFG_WHITE_ON_BLACK
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/* Memory Configuration */
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#define CFG_ENV_OVERWRITE 1
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#define CONFIG_HAS_DATAFLASH 1
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#define CFG_NO_PARALLEL_FLASH 1
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#define CFG_NO_FLASH 1
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#undef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_IS_IN_DATAFLASH 1
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#undef CFG_ENV_IS_IN_NAND
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#define UBOOT_NPCS0
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#undef UBOOT_NPCS1
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#undef UBOOT_NPCS3
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#define SPI_MODE 0
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/* SDRAMC */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */
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#define CFG_MEMTEST_START PHYS_SDRAM
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#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
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/* DataFlash */
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#define CFG_SPI_WRITE_TOUT (50*CFG_HZ)
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/* AC Characteristics */
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/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
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#define DATAFLASH_TCSS (0x1a << 16)
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#define DATAFLASH_TCHS (0x1 << 24)
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#define CFG_MAX_DATAFLASH_BANKS 2
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#define CFG_MAX_DATAFLASH_PAGES 16384
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#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
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#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
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#define CFG_SUPPORT_BLOCK_ERASE 1
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#define CONFIG_NEW_PARTITION 1
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#define NB_DATAFLASH_AREA 6
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/* Parallel Flash Configuration */
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#define PHYS_FLASH_1 0x10000000
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#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
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#define CFG_FLASH_BASE PHYS_FLASH_1
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_MAX_FLASH_SECT 256
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#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
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/* NAND Flash Configuration */
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#define NAND_MAX_CHIPS 1 /* Max number of NAND devices */
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define SECTORSIZE 512
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#define CFG_NAND_BASE 0x40000000
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#define CONFIG_NEW_NAND_CODE
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#undef CFG_NAND_WP
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/*#define AT91_SMART_MEDIA_ALE (1 << 21)*/ /* our ALE is AD21 */
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/*#define AT91_SMART_MEDIA_CLE (1 << 22)*/ /* our CLE is AD22 */
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/* SMC Chip Select 3 Timings for NandFlash K9F1216U0A (samsung)
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* for MASTER_CLOCK = 48000000. They were generated according to
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* K9F1216U0A timings and for MASTER_CLOCK = 48000000.
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* Please refer to SMC section in AT91SAM9261 datasheet to learn how
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* to generate these values.
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*/
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/*
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#define AT91C_SM_NWE_SETUP (0 << 0)
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#define AT91C_SM_NCS_WR_SETUP (0 << 8)
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#define AT91C_SM_NRD_SETUP (0 << 16)
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#define AT91C_SM_NCS_RD_SETUP (0 << 24)
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#define AT91C_SM_NWE_PULSE (2 << 0)
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#define AT91C_SM_NCS_WR_PULSE (3 << 8)
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#define AT91C_SM_NRD_PULSE (2 << 16)
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#define AT91C_SM_NCS_RD_PULSE (4 << 24)
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#define AT91C_SM_NWE_CYCLE (3 << 0)
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#define AT91C_SM_NRD_CYCLE (5 << 16)
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#define AT91C_SM_TDF (1 << 16)
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*/
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/* SMC Chip Select 3 Timings for NandFlash K9F1216U0A (samsung)
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* for MASTER_CLOCK = 100000000. They were generated according to
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* K9F1216U0A timings and for MASTER_CLOCK = 100000000.
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* Please refer to SMC section in AT91SAM9261 datasheet to learn how
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* to generate these values.
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*/
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/* These timings are specific to K9F1216U0A (samsung) */
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/*
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#define AT91C_SM_NWE_SETUP (0 << 0)
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#define AT91C_SM_NCS_WR_SETUP (0 << 8)
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#define AT91C_SM_NRD_SETUP (0 << 16)
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#define AT91C_SM_NCS_RD_SETUP (0 << 24)
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#define AT91C_SM_NWE_PULSE (3 << 0)
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#define AT91C_SM_NCS_WR_PULSE (3 << 8)
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#define AT91C_SM_NRD_PULSE (4 << 16)
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#define AT91C_SM_NCS_RD_PULSE (4 << 24)
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#define AT91C_SM_NWE_CYCLE (5 << 0)
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#define AT91C_SM_NRD_CYCLE (5 << 16)
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*/
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/* These timings are specific to MT29F2G16AAB 256Mb (Micron)
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* at MCK = 100 MHZ
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*/
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/* New NAND commands */
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#define AT91C_SM_NWE_SETUP (0 << 0)
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#define AT91C_SM_NCS_WR_SETUP (0 << 8)
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#define AT91C_SM_NRD_SETUP (0 << 16)
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#define AT91C_SM_NCS_RD_SETUP (0 << 24)
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#define AT91C_SM_NWE_PULSE (4 << 0)
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#define AT91C_SM_NCS_WR_PULSE (6 << 8)
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#define AT91C_SM_NRD_PULSE (3 << 16)
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#define AT91C_SM_NCS_RD_PULSE (5 << 24)
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#define AT91C_SM_NWE_CYCLE (6 << 0)
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#define AT91C_SM_NRD_CYCLE (5 << 16)
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#define AT91C_SM_TDF (1 << 16)
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/*#define CONFIG_MTD_DEBUG 1
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#define CONFIG_MTD_DEBUG_VERBOSE MTD_DEBUG_LEVEL3
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*/
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/* Environment */
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#ifdef CFG_ENV_IS_IN_NAND
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#define CFG_ENV_OFFSET 0x60000 /* environment starts here */
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#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128kB */
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#endif
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#ifdef CFG_ENV_IS_IN_DATAFLASH
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# if defined(UBOOT_NPCS0)
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# define UBOOT_NPCS CFG_DATAFLASH_LOGIC_ADDR_CS0
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# elif defined(UBOOT_NPCS1)
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# define UBOOT_NPCS CFG_DATAFLASH_LOGIC_ADDR_CS1
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# elif defined(UBOOT_NPCS3)
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# define UBOOT_NPCS CFG_DATAFLASH_LOGIC_ADDR_CS3
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# endif
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# define CFG_ENV_OFFSET 0x4200
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# define CFG_ENV_ADDR (UBOOT_NPCS + CFG_ENV_OFFSET)
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# define CFG_ENV_SIZE 0x2000 /* 0x8000 */
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#endif
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#ifdef CFG_ENV_IS_IN_FLASH
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# ifdef CONFIG_BOOTBINFUNC
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# define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
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# define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */
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# else
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# define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
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# define CFG_ENV_SIZE 0x2000 /* 0x8000 */
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# endif
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#endif
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#if CFG_ENV_IS_IN_DATAFLASH | CFG_ENV_IS_IN_FLASH | CFG_ENV_IS_IN_NAND
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#else
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#error "No Environment Defined"
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#endif
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#define KERNEL_1_5_MB
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#define CFG_LOAD_ADDR 0x23f00000 /* default load address */
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#ifdef CONFIG_BOOTBINFUNC
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# define CFG_BOOT_SIZE 0x00 /* 0 KBytes */
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# define CFG_U_BOOT_BASE PHYS_FLASH_1
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# define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */
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#else
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# define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
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# define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
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# define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
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#endif
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#ifndef __ASSEMBLY__
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/*-----------------------------------------------------------------------
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* Board specific extension for bd_info
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*
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* This structure is embedded in the global bd_info (bd_t) structure
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* and can be used by the board specific code (eg board/...)
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*/
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struct bd_info_ext {
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/* helper variable for board environment handling
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*
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* env_crc_valid == 0 => uninitialised
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* env_crc_valid > 0 => environment crc in flash is valid
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* env_crc_valid < 0 => environment crc in flash is invalid
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*/
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int env_crc_valid;
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};
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#endif
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#define CONFIG_STACKSIZE (32*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#error CONFIG_USE_IRQ not supported
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#endif
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#endif
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