eed1670d8a
Previously, it was possible to select an external toolchain that did not support the GCC arch tuning the user had selected. This is problematic because it can lead to confusing error messages during builds [0]. Now, external toolchain selections will be filtered to only those that support the required GCC version specified by the target arch tuning. Note: this patch does not touch the Bootlin toolchain config file as it is generated by a script. Additional note: there is "soft" support for toolchains prior to GCC 4.8 but there are no accompanying BR2_ARCH_NEEDS_GCC_AT_LEAST_X symbols. Instead of adding those, just use BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8 which is the minimum GCC version with claimed support [1]. [0]: https://lists.buildroot.org/pipermail/buildroot/2023-August/671877.html [1]: https://buildroot.org/downloads/manual/manual.html#requirement-mandatory Signed-off-by: Vincent Fazio <vfazio@gmail.com> Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
28 lines
1.1 KiB
Plaintext
28 lines
1.1 KiB
Plaintext
comment "Linaro toolchains available for Cortex-A + EABIhf"
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depends on BR2_arm
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depends on !BR2_ARM_CPU_ARMV7A || !BR2_ARM_EABIHF
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config BR2_TOOLCHAIN_EXTERNAL_LINARO_ARM
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bool "Linaro ARM 2018.05"
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depends on BR2_arm
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depends on BR2_ARM_CPU_ARMV7A || BR2_ARM_CPU_ARMV8A
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depends on BR2_HOSTARCH = "x86_64" || BR2_HOSTARCH = "x86"
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depends on BR2_ARM_EABIHF
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depends on !BR2_ARCH_NEEDS_GCC_AT_LEAST_8
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select BR2_TOOLCHAIN_EXTERNAL_GLIBC
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select BR2_TOOLCHAIN_HAS_SSP
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select BR2_TOOLCHAIN_HAS_NATIVE_RPC
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select BR2_INSTALL_LIBSTDCPP
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select BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_10
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select BR2_TOOLCHAIN_GCC_AT_LEAST_7
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select BR2_TOOLCHAIN_HAS_FORTRAN
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select BR2_TOOLCHAIN_HAS_OPENMP
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help
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Linaro toolchain for the ARM architecture. It uses Linaro
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GCC 2018.05 (based on gcc 7.3.1), Linaro GDB 2018.05 (based on
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GDB 8.1), glibc 2.25, Binutils 2018.05 (based on 2.28). It
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generates code that runs on all Cortex-A profile devices,
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but tuned for the Cortex-A9. The code generated is Thumb 2,
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with the hard floating point calling convention, and uses
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the VFPv3-D16 FPU instructions.
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