From a243628639e12a4bd0a737eac78a12ed240cd137 Mon Sep 17 00:00:00 2001 From: Oleksandr G Zhadan Date: Mon, 18 Jul 2016 10:40:16 -0400 Subject: [PATCH] Arcturus uCP1020 BSP support The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules product featuring a NXP QorIQ P1020 CPU, optionally populated with 1 or 2 Gig-Ethernet PHYs, DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash. Signed-off-by: Oleksandr G Zhadan Signed-off-by: Michael Durrant --- arch/powerpc/boot/dts/ucp1020.dts | 87 ++++++++++++ arch/powerpc/boot/dts/ucp1020.dtsi | 211 ++++++++++++++++++++++++++++++ arch/powerpc/platforms/85xx/Kconfig | 7 + arch/powerpc/platforms/85xx/Makefile | 1 + arch/powerpc/platforms/85xx/ucp1020_som.c | 92 +++++++++++++ 5 files changed, 398 insertions(+) create mode 100644 arch/powerpc/boot/dts/ucp1020.dts create mode 100644 arch/powerpc/boot/dts/ucp1020.dtsi create mode 100644 arch/powerpc/platforms/85xx/ucp1020_som.c diff --git a/arch/powerpc/boot/dts/ucp1020.dts b/arch/powerpc/boot/dts/ucp1020.dts new file mode 100644 index 0000000..291e70a --- /dev/null +++ b/arch/powerpc/boot/dts/ucp1020.dts @@ -0,0 +1,87 @@ +/* + * uCP1020 Tree Source (32-bit address map) + * + * Copyright 2013-2016 Arcturus Networks Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/include/ "fsl/p1020si-pre.dtsi" +/ { + model = "arcturus,uCP1020"; + compatible = "arcturus,uCP1020"; + + memory { + device_type = "memory"; + }; + + lbc: localbus@ffe05000 { + reg = <0 0xffe05000 0 0x1000>; + + /* NOR Flash */ + ranges = <0x0 0x0 0x0 0xec000000 0x04000000>; + }; + + soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; + }; + + pci0: pcie@ffe09000 { + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; + reg = <0 0xffe09000 0 0x1000>; + pcie@0 { + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + pci1: pcie@ffe0a000 { + reg = <0 0xffe0a000 0 0x1000>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; + pcie@0 { + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; +}; + +/include/ "ucp1020.dtsi" +/include/ "fsl/p1020si-post.dtsi" diff --git a/arch/powerpc/boot/dts/ucp1020.dtsi b/arch/powerpc/boot/dts/ucp1020.dtsi new file mode 100644 index 0000000..7cff949 --- /dev/null +++ b/arch/powerpc/boot/dts/ucp1020.dtsi @@ -0,0 +1,211 @@ +/* + * uCP1020 Device Tree Source stub (no addresses or top-level ranges) + * + * Copyright 2013-2016 Arcturus Networks Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&lbc { + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x04000000>; + bank-width = <2>; + device-width = <1>; + + partition@100000 { + /* 7MB - PART 0 */ + reg = <0x00100000 0x00700000>; + label = "0"; + }; + + partition@800000 { + /* 32MB - PART 1 */ + reg = <0x0800000 0x02000000>; + label = "1"; + }; + + partition@2800000 { + /* 8MB - PART 2 */ + reg = <0x02800000 0x00800000>; + label = "2"; + }; + + partition@3000000 { + /* (16MB - 512K) - PART 3 JFFS 2 */ + reg = <0x03000000 0x00f80000>; + label = "3"; + }; + + partition@0 { + /* 512KB - bootloader[u-boot, uCbootloader] */ + reg = <0x0 0x00080000>; + label = "BOOT_SPI"; + }; + + partition@3f80000 { + /* 512KB - bootloade NOR r[u-boot, uCbootloader] */ + reg = <0x03f80000 0x00080000>; + label = "B"; + }; + + partition@80000 { + /* 256KB - bootloaders environment (uCenv) */ + reg = <0x00080000 0x00040000>; + + label = "E"; + }; + + partition@C0000 { + /* 256KB - bootloaders environment (u-boot) */ + reg = <0x000C0000 0x00040000>; + label = "UENV"; + }; + }; +}; + +&soc { + i2c@3000 { + spoc@14 { + compatible = "conexant,cx2070x"; + reg = <0x14>; + }; + }; + + i2c@3100 { + dtt@4C { + compatible = "national,lm90"; + reg = <0x4C>; + }; + }; + + spi@7000 { + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q80bl"; + reg = <0>; + spi-max-frequency = <40000000>; /* input clock */ + + partition@0 { + label = "SPI MBR"; + reg = <0x00000000 0x00002000>; + read-only; + }; + partition@2000 { + label = "SPI ENV"; + reg = <0x00002000 0x00006000>; + read-only; + }; + partition@8000 { + label = "SPI FS"; + reg = <0x00008000 0x000F8000>; + }; + }; + flash@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl008k"; + reg = <3>; + spi-max-frequency = <40000000>; /* input clock */ + partition@0 { + label = "SPI USER"; + reg = <0x00000000 0x00100000>; + }; + }; + }; + + usb@22000 { + phy_type = "ulpi"; + dr_mode = "host"; + }; + + mdio@24000 { + phy0: ethernet-phy@4 { + interrupt-parent = <&mpic>; + interrupts = <4 1>; + reg = <0x04>; + }; + + phy1: ethernet-phy@6 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <0x6>; + }; + }; + + enet0: ethernet@b0000 { + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + }; + + enet1: ethernet@b1000 { + status = "disabled"; + }; + + enet2: ethernet@b2000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; + + gpio0: gpio@f000 { + compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio"; + reg = <0xf000 0x1000>; + interrupts = <47 2>; + interrupt-parent = <&mpic>; + #gpio-cells = <2>; + gpio-controller; + }; + + gpio-leds { + compatible = "gpio-leds"; + gpio5 { + label = "led1"; /* LED15 */ + gpios = <&gpio0 5 0>; + }; + gpio12 { + label = "led2"; /* LED16 */ + gpios = <&gpio0 12 0>; + }; + gpio13 { + label = "led3"; /* LED17 */ + gpios = <&gpio0 13 0>; + }; + gpio7 { + label = "led4"; /* LED18 */ + gpios = <&gpio0 7 0>; + }; + gpio6 { + label = "led5"; /* LED19 */ + gpios = <&gpio0 6 0>; + }; + }; +}; diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 2fb4b24..81a944f 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -241,6 +241,13 @@ config SGY_CTS1000 help Enable this to support functionality in Servergy's CTS-1000 systems. +config UCP1020_SOM + bool "Arcturus uCP1020 Rev.1.3 System on Module" + select DEFAULT_UIMAGE + help + This option enables support for the Arcturus Networks Inc. + uCP1020 System on Module. + config MVME2500 bool "Artesyn MVME2500" select DEFAULT_UIMAGE diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index 1fe7fb9..84f2b9a 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile @@ -31,4 +31,5 @@ obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o obj-$(CONFIG_GE_IMP3A) += ge_imp3a.o obj-$(CONFIG_PPC_QEMU_E500) += qemu_e500.o obj-$(CONFIG_SGY_CTS1000) += sgy_cts1000.o +obj-$(CONFIG_UCP1020_SOM) += ucp1020_som.o obj-$(CONFIG_MVME2500) += mvme2500.o diff --git a/arch/powerpc/platforms/85xx/ucp1020_som.c b/arch/powerpc/platforms/85xx/ucp1020_som.c new file mode 100644 index 0000000..777e8ad --- /dev/null +++ b/arch/powerpc/platforms/85xx/ucp1020_som.c @@ -0,0 +1,92 @@ +/* + * Arcturus Networks Inc. uCP1020 module Setup + * + * Copyright 2014-2016 Arcturus Networks Inc. + * + * by Oleksandr G Zhadan & Michael Durrant (www.ArcturusNetworks.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "smp.h" + +#include "mpc85xx.h" + +void __init ucp1020_som_pic_init(void) +{ + struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | + MPIC_SINGLE_DEST_CPU, + 0, 256, " OpenPIC "); + + BUG_ON(mpic == NULL); + + mpic_init(mpic); +} + +/* + * Setup the architecture + */ +static void __init ucp1020_som_setup_arch(void) +{ + if (ppc_md.progress) + ppc_md.progress("uCP1020_SoM_setup_arch()", 0); + + mpc85xx_smp_init(); + + fsl_pci_assign_primary(); + pr_info("\n\t%s (http://www.arcturusnetworks.com)\n", ppc_md.name); +} + +machine_arch_initcall(ucp1020, mpc85xx_common_publish_devices); +machine_arch_initcall(ucp1020, swiotlb_setup_bus_notifier); + +/* + * Called very early, device-tree isn't unflattened + */ +static int __init ucp1020_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + if (of_flat_dt_is_compatible(root, "arcturus,uCP1020")) + return 1; + return 0; +} + +define_machine(ucp1020) { + .name = "uCP1020 SoM - Arcturus Networks Inc.", + .probe = ucp1020_probe, + .setup_arch = ucp1020_som_setup_arch, + .init_IRQ = ucp1020_som_pic_init, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif + .get_irq = mpic_get_irq, + .restart = fsl_rstcr_restart, + .calibrate_decr = generic_calibrate_decr, +#ifdef DEBUG + .progress = udbg_progress, +#endif +}; -- 2.1.4