This commits adds support for building a RISC-V toolchain with the
vector extension, available since gcc 12.
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Since gcc 12, the default RISC-V ISA spec version was bump to 20191213 [1].
This bump introduces a major compatibility issue: support for the csr read/write
(csrr*/csrw*) instructions and fence.i instruction has been separated
from the "I" extension, becoming two standalone extensions: Zicsr and
Zifencei. gcc now has specific -march suffixes to enable those
extensions (_zicsr and _zifencei). If they are not used and code that
uses these instructions is built, one would get errors such as
unrecognized opcode "csrr" (or "fence.i").
For example, without Zifencei we can't build the opensbi
bootloader[2]:
opensbi-1.0/lib/sbi/sbi_tlb.c: Assembler messages:
opensbi-1.0/lib/sbi/sbi_tlb.c:190: Error: unrecognized opcode `fence.i', extension `zifencei' required
As a workaround, the opensbi build system has been patched [3] to use
-march=rv64imafdc_zicsr_zifencei when needed. This workaround doesn't
work in Buildroot due to the local patch
0001-Makefile-Don-t-specify-mabi-or-march.patch which removes -march
from CFLAGS.
In the context of Buildroot, we have decided for now to assume that
all RISC-V cores that are Linux capable will implement the Zicsr and
Zifencei extensions: it is in fact the case today ase these extensions
were part of the I extension, that all cores support. OpenSBI and
Linux are making the same assumption (see [5]).
Therefore, when gcc >= 12, the -march value gets appended with
_zicsr_zifencei.
[1] https://gcc.gnu.org/gcc-12/changes.html
[2] https://github.com/riscv-software-src/opensbi/blob/v0.9/lib/sbi/sbi_tlb.c#L173
[3] 5d53b55aa7
[4] https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/aE1ZeHHCYf4
[5] http://lists.busybox.net/pipermail/buildroot/2022-July/646698.html
Signed-off-by: Romain Naour <romain.naour@gmail.com>
Cc: Mark Corbin <mark@dibsco.co.uk>
[Thomas: add comment in .mk file, rework commit log]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
This enables a riscv32 system to be built with a Buildroot generated
toolchain (gcc >= 7.x, binutils >= 2.30, glibc only).
This requires a custom version of glibc 2.26 from the riscv-glibc
repository. Note that there are no tags in this repository, so the
glibc version just consists of the 40 character commit id string.
Thanks to Fabrice Bellard for pointing me towards the 32-bit glibc
repository and for providing the necessary patch to get it to build.
Signed-off-by: Mark Corbin <mark.corbin@embecosm.com>
Reviewed-by: Matt Weber <matthew.weber@rockwellcollins.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
This enables a riscv64 system to be built with a Buildroot generated
toolchain (gcc >= 7.x, binutils >= 2.30, glibc only).
This configuration has been used to successfully build a qemu-bootable
riscv-linux-4.15 kernel (https://github.com/riscv/riscv-linux.git).
Signed-off-by: Mark Corbin <mark.corbin@embecosm.com>
[Thomas:
- simplify arch.mk.riscv by directly setting GCC_TARGET_ARCH
- simplify glibc.mk changes by using GLIBC_CONF_ENV.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
