From ffcefb3a75d622fb283ec9a0e09b127de7c39110 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 25 Jan 2022 00:01:11 +0100 Subject: [PATCH] arch/Config.in.x86: add goldmont, goldmont-plus, tremont, cascadelake, tigerlake CPU variants These were added in gcc 9.x. The goldmont, goldmont-plus and tremont are for the low-power CPUs. While cascadelake and tigerlake are for the high-end ones. Signed-off-by: Thomas Petazzoni Signed-off-by: Yann E. MORIN --- arch/Config.in.x86 | 61 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/Config.in.x86 b/arch/Config.in.x86 index e9c55bb319..dffc9a74d3 100644 --- a/arch/Config.in.x86 +++ b/arch/Config.in.x86 @@ -302,6 +302,36 @@ config BR2_x86_silvermont select BR2_X86_CPU_HAS_SSE4 select BR2_X86_CPU_HAS_SSE42 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 +config BR2_x86_goldmont + bool "goldmont" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 + select BR2_X86_CPU_HAS_SSE4 + select BR2_X86_CPU_HAS_SSE42 + select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 +config BR2_x86_goldmont_plus + bool "goldmont-plus" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 + select BR2_X86_CPU_HAS_SSE4 + select BR2_X86_CPU_HAS_SSE42 + select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 +config BR2_x86_tremont + bool "tremont" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 + select BR2_X86_CPU_HAS_SSE4 + select BR2_X86_CPU_HAS_SSE42 + select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 config BR2_x86_skylake_avx512 bool "skylake-avx512" select BR2_X86_CPU_HAS_MMX @@ -354,6 +384,32 @@ config BR2_x86_icelake_server select BR2_X86_CPU_HAS_AVX2 select BR2_X86_CPU_HAS_AVX512 select BR2_ARCH_NEEDS_GCC_AT_LEAST_8 +config BR2_x86_cascadelake + bool "cascadelake" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 + select BR2_X86_CPU_HAS_SSE4 + select BR2_X86_CPU_HAS_SSE42 + select BR2_X86_CPU_HAS_AVX + select BR2_X86_CPU_HAS_AVX2 + select BR2_X86_CPU_HAS_AVX512 + select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 +config BR2_x86_tigerlake + bool "tigerlake" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 + select BR2_X86_CPU_HAS_SSE4 + select BR2_X86_CPU_HAS_SSE42 + select BR2_X86_CPU_HAS_AVX + select BR2_X86_CPU_HAS_AVX2 + select BR2_X86_CPU_HAS_AVX512 + select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 config BR2_x86_k6 bool "k6" depends on !BR2_x86_64 @@ -486,10 +542,15 @@ config BR2_GCC_TARGET_ARCH default "bonnel" if BR2_x86_bonnel default "westmere" if BR2_x86_westmere default "silvermont" if BR2_x86_silvermont + default "goldmont" if BR2_x86_goldmont + default "goldmont-plus" if BR2_x86_goldmont_plus + default "tremont" if BR2_x86_tremont default "skylake-avx512" if BR2_x86_skylake_avx512 default "cannonlake" if BR2_x86_cannonlake default "icelake-client" if BR2_x86_icelake_client default "icelake-server" if BR2_x86_icelake_server + default "cascadelake" if BR2_x86_cascadelake + default "tigerlake" if BR2_x86_tigerlake default "k8" if BR2_x86_opteron default "k8-sse3" if BR2_x86_opteron_sse3 default "barcelona" if BR2_x86_barcelona