board/andes/ae350: add support for Andes AE350
This patch provides defconfig and basic support for Andes 45 series RISC-V architecture on AE350 platform. http://www.andestech.com/en/products-solutions/andeshape-platforms/ae350-axi-based-platform-pre-integrated-with-n25f-nx25f-a25-ax25/ Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Signed-off-by: Alan Kao <alankao@andestech.com> Reviewed-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Tested-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
This commit is contained in:
Yu Chien Peter Lin
Arnout Vandecappelle (Essensium/Mind)
parent
48bdd83741
commit
fc22c3ce40
274
board/andes/ae350/ae350.dts
Executable file
274
board/andes/ae350/ae350.dts
Executable file
@ -0,0 +1,274 @@
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "andestech,ae350";
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model = "andestech,ax45";
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aliases {
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uart0 = &serial0;
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spi0 = &spi;
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};
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chosen {
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bootargs = "console=ttyS0,38400n8 earlycon=sbi debug loglevel=7";
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stdout-path = "uart0:38400n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <60000000>;
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CPU0: cpu@0 {
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-1p1xdsp0p0";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv48";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-block-size = <64>;
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i-cache-line-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-line-size = <64>;
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next-level-cache = <&L2>;
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CPU0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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reg = <1>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-1p1xdsp0p0";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv48";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-block-size = <64>;
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i-cache-line-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-line-size = <64>;
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next-level-cache = <&L2>;
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CPU1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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reg = <2>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-1p1xdsp0p0";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv48";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-block-size = <64>;
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i-cache-line-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-line-size = <64>;
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next-level-cache = <&L2>;
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CPU2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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reg = <3>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-1p1xdsp0p0";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv48";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <256>;
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i-cache-block-size = <64>;
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i-cache-line-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-line-size = <64>;
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next-level-cache = <&L2>;
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CPU3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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L2: l2-cache@e0500000 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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reg = <0x00000000 0xe0500000 0x00000000 0x00001000>;
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andes,inst-prefetch = <3>;
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andes,data-prefetch = <3>;
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// The value format is <XRAMOCTL XRAMICTL>
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andes,tag-ram-ctl = <0 0>;
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andes,data-ram-ctl = <0 0>;
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};
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memory@0 {
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reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
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device_type = "memory";
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "andestech,riscv-ae350-soc", "simple-bus";
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ranges;
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plic0: interrupt-controller@e4000000 {
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compatible = "riscv,plic0";
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reg = <0x00000000 0xe4000000 0x00000000 0x02000000>;
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interrupts-extended = < &CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9 &CPU2_intc 11 &CPU2_intc 9 &CPU3_intc 11 &CPU3_intc 9>;
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interrupt-controller;
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#address-cells = <2>;
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#interrupt-cells = <2>;
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riscv,ndev = <71>;
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};
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plic1: interrupt-controller@e6400000 {
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compatible = "riscv,plic1";
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reg = <0x00000000 0xe6400000 0x00000000 0x00400000>;
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interrupts-extended = < &CPU0_intc 3 &CPU1_intc 3 &CPU2_intc 3 &CPU3_intc 3>;
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interrupt-controller;
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#address-cells = <2>;
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#interrupt-cells = <2>;
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riscv,ndev = <4>;
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};
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plmt0: plmt0@e6000000 {
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compatible = "riscv,plmt0";
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reg = <0x00000000 0xe6000000 0x00000000 0x00100000>;
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interrupts-extended = < &CPU0_intc 7 &CPU1_intc 7 &CPU2_intc 7 &CPU3_intc 7>;
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};
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spiclk: virt_100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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timer0: timer@f0400000 {
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compatible = "andestech,atcpit100";
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reg = <0x00000000 0xf0400000 0x00000000 0x00001000>;
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interrupts = <3 4>;
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interrupt-parent = <&plic0>;
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clock-frequency = <60000000>;
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};
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pwm: pwm@f0400000 {
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compatible = "andestech,atcpit100-pwm";
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reg = <0x00000000 0xf0400000 0x00000000 0x00001000>;
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interrupts = <3 4>;
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interrupt-parent = <&plic0>;
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clock-frequency = <60000000>;
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pwm-cells = <2>;
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};
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wdt: wdt@f0500000 {
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compatible = "andestech,atcwdt200";
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reg = <0x00000000 0xf0500000 0x00000000 0x00001000>;
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interrupts = <3 4>;
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interrupt-parent = <&plic0>;
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clock-frequency = <15000000>;
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};
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serial0: serial@f0300000 {
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compatible = "andestech,uart16550", "ns16550a";
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reg = <0x00000000 0xf0300000 0x00000000 0x00001000>;
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interrupts = <9 4>;
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interrupt-parent = <&plic0>;
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clock-frequency = <19660800>;
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reg-shift = <2>;
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reg-offset = <32>;
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no-loopback-test = <1>;
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};
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rtc0: rtc@f0600000 {
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compatible = "andestech,atcrtc100";
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reg = <0x00000000 0xf0600000 0x00000000 0x00001000>;
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interrupts = <1 4 2 4>;
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interrupt-parent = <&plic0>;
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wakeup-source;
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};
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gpio: gpio@f0700000 {
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compatible = "andestech,atcgpio100";
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reg = <0x00000000 0xf0700000 0x00000000 0x00001000>;
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interrupts = <7 4>;
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interrupt-parent = <&plic0>;
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wakeup-source;
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};
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mac0: mac@e0100000 {
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compatible = "andestech,atmac100";
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reg = <0x00000000 0xe0100000 0x00000000 0x00001000>;
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interrupts = <19 4>;
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interrupt-parent = <&plic0>;
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dma-coherent;
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};
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smu: smu@f0100000 {
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compatible = "andestech,atcsmu";
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reg = <0x00000000 0xf0100000 0x00000000 0x00001000>;
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};
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mmc0: mmc@f0e00000 {
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compatible = "andestech,atfsdc010";
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reg = <0x00000000 0xf0e00000 0x00000000 0x00001000>;
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interrupts = <18 4>;
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interrupt-parent = <&plic0>;
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clock-freq-min-max = <400000 100000000>;
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max-frequency = <100000000>;
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fifo-depth = <16>;
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cap-sd-highspeed;
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dma-coherent;
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};
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dma0: dma@f0c00000 {
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compatible = "andestech,atcdmac300";
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reg = <0x00000000 0xf0c00000 0x00000000 0x00001000>;
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interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
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interrupt-parent = <&plic0>;
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dma-channels = <8>;
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};
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lcd0: lcd@e0200000 {
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compatible = "andestech,atflcdc100";
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reg = <0x00000000 0xe0200000 0x00000000 0x00001000>;
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interrupts = <20 4>;
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interrupt-parent = <&plic0>;
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dma-coherent;
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};
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pmu: pmu {
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compatible = "riscv,andes-pmu";
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device_type = "pmu";
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};
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spi: spi@f0b00000 {
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compatible = "andestech,atcspi200";
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reg = <0x00000000 0xf0b00000 0x00000000 0x00001000>;
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interrupts = <4 4>;
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interrupt-parent = <&plic0>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <1>;
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clocks = <&spiclk>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0x00000000>;
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spi-max-frequency = <50000000>;
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spi-cpol;
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spi-cpha;
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};
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};
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};
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};
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26
board/andes/ae350/genimage_sdcard.cfg
Normal file
26
board/andes/ae350/genimage_sdcard.cfg
Normal file
@ -0,0 +1,26 @@
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image boot.vfat {
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vfat {
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files = {
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"u-boot-spl.bin",
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"u-boot.itb",
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"ae350.dtb",
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}
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}
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size = 2M
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}
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image sdcard.img {
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hdimage {
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}
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partition boot {
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partition-type = 0xC
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image = "boot.vfat"
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}
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partition rootfs {
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partition-type = 0x83
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bootable = true
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image = "rootfs.ext4"
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}
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}
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@ -0,0 +1,29 @@
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From 3ccb71eeca42dbcd5e4d00ae1877a489ae82598d Mon Sep 17 00:00:00 2001
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From: Yu Chien Peter Lin <peterlin@andestech.com>
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Date: Wed, 29 Dec 2021 16:04:54 +0800
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Subject: [PATCH] Disable PIC explicitly for assembling
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This patch is necessary if the fw_dynamic load address
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is not equal to link address.
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However, they are equal currently, since we include an u-boot
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patch for preventing fw_dynamic relocation.
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Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
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---
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Makefile | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/Makefile b/Makefile
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index d6f097d..441518d 100644
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--- a/Makefile
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+++ b/Makefile
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@@ -225,6 +225,7 @@ ASFLAGS += -mcmodel=$(PLATFORM_RISCV_CODE_MODEL)
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ASFLAGS += $(GENFLAGS)
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ASFLAGS += $(platform-asflags-y)
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ASFLAGS += $(firmware-asflags-y)
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+ASFLAGS += -fno-pic
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ARFLAGS = rcs
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--
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2.25.1
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@ -0,0 +1,25 @@
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From 325328f4204b40b1fcc8db3b46c7c8805710d21c Mon Sep 17 00:00:00 2001
|
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From: Yu Chien Peter Lin <peterlin@andestech.com>
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Date: Thu, 30 Dec 2021 08:47:34 +0800
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Subject: [PATCH] Enable cache for opensbi jump mode
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Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
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---
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firmware/fw_base.S | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/firmware/fw_base.S b/firmware/fw_base.S
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index ab33e11..155d230 100644
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--- a/firmware/fw_base.S
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+++ b/firmware/fw_base.S
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@@ -46,6 +46,8 @@
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.globl _start
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.globl _start_warm
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_start:
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+ li t0, 0x80003
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+ csrw 0x7ca, t0
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/* Find preferred boot HART id */
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MOV_3R s0, a0, s1, a1, s2, a2
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call fw_boot_hart
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--
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2.25.1
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@ -0,0 +1,27 @@
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From ea4675215b53d16a72d29b8a6fc6a86cccf59cf0 Mon Sep 17 00:00:00 2001
|
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From: Yu Chien Peter Lin <peterlin@andestech.com>
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Date: Wed, 5 Jan 2022 11:00:59 +0800
|
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Subject: [PATCH] Fix mmc no partition table error
|
||||
|
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Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
|
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---
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drivers/mmc/ftsdc010_mci.c | 4 ----
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1 file changed, 4 deletions(-)
|
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|
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diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c
|
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index 570d54cf..3b1e0aa0 100644
|
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--- a/drivers/mmc/ftsdc010_mci.c
|
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+++ b/drivers/mmc/ftsdc010_mci.c
|
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@@ -438,10 +438,6 @@ static int ftsdc010_mmc_probe(struct udevice *dev)
|
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return ret;
|
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#endif
|
||||
|
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- if (dev_read_bool(dev, "cap-mmc-highspeed") || \
|
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- dev_read_bool(dev, "cap-sd-highspeed"))
|
||||
- chip->caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
|
||||
-
|
||||
ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
|
||||
priv->minmax[1] , priv->minmax[0]);
|
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chip->mmc = &plat->mmc;
|
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--
|
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2.25.1
|
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@ -0,0 +1,27 @@
|
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From 4c0c5378d032f2f95577585935624baf7b4decf3 Mon Sep 17 00:00:00 2001
|
||||
From: Yu Chien Peter Lin <peterlin@andestech.com>
|
||||
Date: Wed, 5 Jan 2022 11:02:26 +0800
|
||||
Subject: [PATCH] Prevent fw_dynamic from relocation
|
||||
|
||||
This patch prevents OpenSBI relocation, load fw_dynamic to link address
|
||||
|
||||
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
|
||||
---
|
||||
board/AndesTech/ax25-ae350/Kconfig | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
|
||||
index e50f505a..385c4c11 100644
|
||||
--- a/board/AndesTech/ax25-ae350/Kconfig
|
||||
+++ b/board/AndesTech/ax25-ae350/Kconfig
|
||||
@@ -25,7 +25,7 @@ config SPL_TEXT_BASE
|
||||
default 0x800000
|
||||
|
||||
config SPL_OPENSBI_LOAD_ADDR
|
||||
- default 0x01000000
|
||||
+ default 0x0
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
--
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||||
2.25.1
|
||||
@ -0,0 +1,26 @@
|
||||
From 3d09501175ae6f5e3f6520b48b1358226a99ff16 Mon Sep 17 00:00:00 2001
|
||||
From: Yu Chien Peter Lin <peterlin@andestech.com>
|
||||
Date: Wed, 5 Jan 2022 18:17:39 +0800
|
||||
Subject: [PATCH] Fix u-boot proper booting issue
|
||||
|
||||
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
|
||||
---
|
||||
arch/riscv/cpu/start.S | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
|
||||
index 76850ec9..2ccda4f5 100644
|
||||
--- a/arch/riscv/cpu/start.S
|
||||
+++ b/arch/riscv/cpu/start.S
|
||||
@@ -139,7 +139,9 @@ call_harts_early_init:
|
||||
* accesses gd).
|
||||
*/
|
||||
mv gp, s0
|
||||
+#if !CONFIG_IS_ENABLED(RISCV_SMODE)
|
||||
bnez tp, secondary_hart_loop
|
||||
+#endif
|
||||
#endif
|
||||
|
||||
jal board_init_f_init_reserve
|
||||
--
|
||||
2.25.1
|
||||
@ -0,0 +1,25 @@
|
||||
From 3847a959ac4c07facbd80104ca5fa6a91fad5f35 Mon Sep 17 00:00:00 2001
|
||||
From: Yu Chien Peter Lin <peterlin@andestech.com>
|
||||
Date: Thu, 6 Jan 2022 13:50:07 +0800
|
||||
Subject: [PATCH] Enable printing OpenSBI boot logo
|
||||
|
||||
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
|
||||
---
|
||||
include/opensbi.h | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/include/opensbi.h b/include/opensbi.h
|
||||
index d812cc8c..91fb8fd9 100644
|
||||
--- a/include/opensbi.h
|
||||
+++ b/include/opensbi.h
|
||||
@@ -20,7 +20,7 @@
|
||||
|
||||
enum sbi_scratch_options {
|
||||
/** Disable prints during boot */
|
||||
- SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
|
||||
+ SBI_SCRATCH_NO_BOOT_PRINTS = 0,
|
||||
};
|
||||
|
||||
/** Representation dynamic info passed by previous booting stage */
|
||||
--
|
||||
2.25.1
|
||||
3
board/andes/ae350/post-build.sh
Executable file
3
board/andes/ae350/post-build.sh
Executable file
@ -0,0 +1,3 @@
|
||||
#!/bin/sh
|
||||
cp $BINARIES_DIR/Image $TARGET_DIR/boot
|
||||
cp $BINARIES_DIR/ae350.dtb $TARGET_DIR/boot
|
||||
65
board/andes/ae350/readme.txt
Normal file
65
board/andes/ae350/readme.txt
Normal file
@ -0,0 +1,65 @@
|
||||
Intro
|
||||
=====
|
||||
|
||||
Andestech AE350 Platform
|
||||
|
||||
The AE350 prototype demonstrates the AE350 platform on the FPGA.
|
||||
|
||||
How to build it
|
||||
===============
|
||||
|
||||
Configure Buildroot
|
||||
-------------------
|
||||
|
||||
$ make andes_ae350_45_defconfig
|
||||
|
||||
If you want to customize your configuration:
|
||||
|
||||
$ make menuconfig
|
||||
|
||||
Build everything
|
||||
----------------
|
||||
Note: you will need to access to the network, since Buildroot will
|
||||
download the packages' sources.
|
||||
|
||||
$ make
|
||||
|
||||
Result of the build
|
||||
-------------------
|
||||
|
||||
After building, you should obtain the following files:
|
||||
|
||||
output/images/
|
||||
|-- ae350.dtb
|
||||
|-- boot.vfat
|
||||
|-- fw_dynamic.bin
|
||||
|-- fw_dynamic.elf
|
||||
|-- fw_jump.bin
|
||||
|-- fw_jump.elf
|
||||
|-- Image
|
||||
|-- rootfs.ext2
|
||||
|-- rootfs.ext4 -> rootfs.ext2
|
||||
|-- sdcard.img
|
||||
|-- u-boot-spl.bin
|
||||
`-- u-boot.itb
|
||||
|
||||
Copy the sdcard.img to a SD card with "dd":
|
||||
|
||||
$ sudo dd if=sdcard.img of=/dev/sdX bs=4096
|
||||
$ sudo sync
|
||||
|
||||
Your SD card partition should be:
|
||||
|
||||
Disk /dev/sdb: 14.48 GiB, 15552479232 bytes, 30375936 sectors
|
||||
Disk model: Multi-Card
|
||||
Units: sectors of 1 * 512 = 512 bytes
|
||||
Sector size (logical/physical): 512 bytes / 512 bytes
|
||||
I/O size (minimum/optimal): 512 bytes / 512 bytes
|
||||
Disklabel type: dos
|
||||
Disk identifier: 0x00000000
|
||||
|
||||
Device Boot Start End Sectors Size Id Type
|
||||
/dev/sdb1 1 4096 4096 2M c W95 FAT32 (LBA)
|
||||
/dev/sdb2 * 4097 126976 122880 60M 83 Linux
|
||||
|
||||
Insert SD card and reset the board, it should boot Linux from mmc.
|
||||
@ -0,0 +1,4 @@
|
||||
label linux
|
||||
kernel /boot/Image
|
||||
fdt /boot/ae350.dtb
|
||||
append earlycon=sbi root=/dev/mmcblk0p2 rootwait
|
||||
5
board/andes/ae350/uboot.config.fragment
Normal file
5
board/andes/ae350/uboot.config.fragment
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_SPL_FS_FAT=y
|
||||
CONFIG_SPL_MMC=y
|
||||
# CONFIG_SPL_RAM_SUPPORT is not set
|
||||
# CONFIG_OF_BOARD is not set
|
||||
CONFIG_OF_SEPARATE=y
|
||||
43
configs/andes_ae350_45_defconfig
Normal file
43
configs/andes_ae350_45_defconfig
Normal file
@ -0,0 +1,43 @@
|
||||
BR2_riscv=y
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVF=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVD=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=y
|
||||
BR2_GLOBAL_PATCH_DIR="board/andes/ae350/patches"
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_10=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="ttyS0"
|
||||
BR2_ROOTFS_OVERLAY="board/andes/ae350/rootfs_overlay"
|
||||
BR2_ROOTFS_POST_BUILD_SCRIPT="board/andes/ae350/post-build.sh"
|
||||
BR2_ROOTFS_POST_IMAGE_SCRIPT="support/scripts/genimage.sh"
|
||||
BR2_ROOTFS_POST_SCRIPT_ARGS="-c board/andes/ae350/genimage_sdcard.cfg"
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_GIT=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_REPO_URL="https://github.com/andestech/linux.git"
|
||||
BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="v5.10.84-ae350_45"
|
||||
BR2_LINUX_KERNEL_DEFCONFIG="ae350_rv64_smp"
|
||||
BR2_LINUX_KERNEL_DTS_SUPPORT=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_DTS_PATH="board/andes/ae350/ae350.dts"
|
||||
BR2_TARGET_ROOTFS_EXT2=y
|
||||
BR2_TARGET_ROOTFS_EXT2_4=y
|
||||
# BR2_TARGET_ROOTFS_TAR is not set
|
||||
BR2_TARGET_OPENSBI=y
|
||||
BR2_TARGET_OPENSBI_PLAT="andes/ae350"
|
||||
BR2_TARGET_UBOOT=y
|
||||
BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
|
||||
BR2_TARGET_UBOOT_CUSTOM_VERSION=y
|
||||
BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2022.01"
|
||||
BR2_TARGET_UBOOT_BOARD_DEFCONFIG="ae350_rv64_spl_xip"
|
||||
BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES="board/andes/ae350/uboot.config.fragment"
|
||||
BR2_TARGET_UBOOT_NEEDS_PYTHON3=y
|
||||
BR2_TARGET_UBOOT_NEEDS_PYLIBFDT=y
|
||||
BR2_TARGET_UBOOT_NEEDS_OPENSSL=y
|
||||
BR2_TARGET_UBOOT_NEEDS_OPENSBI=y
|
||||
# BR2_TARGET_UBOOT_FORMAT_BIN is not set
|
||||
BR2_TARGET_UBOOT_FORMAT_CUSTOM=y
|
||||
BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot.itb"
|
||||
BR2_TARGET_UBOOT_SPL=y
|
||||
BR2_TARGET_UBOOT_CUSTOM_MAKEOPTS="ARCH_FLAGS=-march=rv64imafdc"
|
||||
BR2_PACKAGE_HOST_DOSFSTOOLS=y
|
||||
BR2_PACKAGE_HOST_GENIMAGE=y
|
||||
BR2_PACKAGE_HOST_MTOOLS=y
|
||||
Loading…
Reference in New Issue
Block a user