From eeace1cc13ce09a0c88ce177465b836d6eb58298 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Sun, 9 Jan 2022 09:01:23 +0100 Subject: [PATCH] arch/Config.in.x86: add support for x86-64-v2, x86-64-v3, x86-64-v4 In the face of the vast amount of x86-64 CPU architecture variants, Linux distributions have worked together to define "micro-architecture levels" in the x86-64 psABI, called x86-64-v2, x86-64-v3 and x86-64-v4. They standardize a set of CPU features, and GCC since its version 11.x has support for these micro-architecture levels as -march= options. It makes sense to support them in Buildroot, especially for those who want to build toolchains that aim at targeting a reasonably broad family of x86-64 processors. It only really makes sense to use as 64-bit CPUs, and not as 32-bit ones, so we guard them behind BR2_x86_64. More details: https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex https://developers.redhat.com/blog/2021/01/05/building-red-hat-enterprise-linux-9-for-the-x86-64-v2-microarchitecture-level https://www.phoronix.com/scan.php?page=news_item&px=GCC-11-x86-64-Feature-Levels https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=59482fa1e7243bd905c7e27c92ae2b89c79fff87 Signed-off-by: Thomas Petazzoni [yann.morin.1998@free.fr: - they are x86-64-only CPUs - add gcc commit URL ] Signed-off-by: Yann E. MORIN --- arch/Config.in.x86 | 63 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/Config.in.x86 b/arch/Config.in.x86 index 34564c1ed1..0ba9ecbcea 100644 --- a/arch/Config.in.x86 +++ b/arch/Config.in.x86 @@ -92,6 +92,66 @@ config BR2_x86_x86_64 "Generic CPU with 64-bit extensions" by the GCC documentation. It is a 64-bit CPU with MMX, SSE and SSE2 support. +config BR2_x86_x86_64_v2 + bool "x86-64-v2" + depends on BR2_x86_64 + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 + select BR2_X86_CPU_HAS_SSE4 + select BR2_X86_CPU_HAS_SSE42 + select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 + help + This option corresponds to the x86-64-v2 micro-architecture + level, as defined by the x86-64 psABI document, see + https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex. + + It is close to the Nehalem CPU architecture, and is + applicable for CPUs that support CMPXCHG16B, LAHF-SAHF, + POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3. +config BR2_x86_x86_64_v3 + bool "x86-64-v3" + depends on BR2_x86_64 + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 + select BR2_X86_CPU_HAS_SSE4 + select BR2_X86_CPU_HAS_SSE42 + select BR2_X86_CPU_HAS_AVX + select BR2_X86_CPU_HAS_AVX2 + select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 + help + This option corresponds to the x86-64-v3 micro-architecture + level, as defined by the x86-64 psABI document, see + https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex. + + It is close to the Haswell CPU architecture, and is + applicable for CPUs that support all of x86-64-v2 plus AVX, + AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE. +config BR2_x86_x86_64_v4 + bool "x86-64-v4" + depends on BR2_x86_64 + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 + select BR2_X86_CPU_HAS_SSE4 + select BR2_X86_CPU_HAS_SSE42 + select BR2_X86_CPU_HAS_AVX + select BR2_X86_CPU_HAS_AVX2 + select BR2_ARCH_NEEDS_GCC_AT_LEAST_11 + help + This option corresponds to the x86-64-v4 micro-architecture + level, as defined by the x86-64 psABI document, see + https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex. + + It is applicable for CPUs that support all of x86-64-v3 plus + AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL. config BR2_x86_nocona bool "nocona" select BR2_X86_CPU_HAS_MMX @@ -293,6 +353,9 @@ config BR2_GCC_TARGET_ARCH default "pentium4" if BR2_x86_pentium4 default "prescott" if BR2_x86_prescott default "x86-64" if BR2_x86_x86_64 + default "x86-64-v2" if BR2_x86_x86_64_v2 + default "x86-64-v3" if BR2_x86_x86_64_v3 + default "x86-64-v4" if BR2_x86_x86_64_v4 default "nocona" if BR2_x86_nocona default "core2" if BR2_x86_core2 default "corei7" if BR2_x86_corei7