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configs/octavo_osd32mp1_red: update BSP components

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Update description:
  TF-A to v2.4-stm32mp-r1
  U-boot to version v2020.10-stm32mp-r2.1
  Linux to v5.10-stm32mp-r2.1

This patch also updates U-boot to to use FIP image.

Reference:

  https://octavosystems.com/octavo_products/osd32mp1-red/

The device tree blobs, and the U-boot patches come from Octavo System:

  https://github.com/octavosystems/meta-octavo-osd32mp1

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
This commit is contained in:
Kory Maincent 2022-10-05 09:58:13 +02:00 committed by Thomas Petazzoni
parent 9e698c552b
commit 8f088e6841
10 changed files with 1511 additions and 3514 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
board/octavo/osd32mp1-red/genimage.cfg
View File

@ -4,15 +4,15 @@ image sdcard.img {
}
partition fsbl1 {
image = "tf-a-osd32mp1-red.stm32"
image = "tf-a-stm32mp157c-osd32mp1-red.stm32"
}
partition fsbl2 {
image = "tf-a-osd32mp1-red.stm32"
image = "tf-a-stm32mp157c-osd32mp1-red.stm32"
}
partition ssbl {
image = "u-boot.stm32"
partition fip {
image = "fip.bin"
size = 2M
}

491
board/octavo/osd32mp1-red/linux-dts/osd32mp1-red.dts → board/octavo/osd32mp1-red/linux-dts/stm32mp157c-osd32mp1-red.dts
View File

@ -1,29 +1,26 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (C) STMicroelectronics 2020 - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics.
*/
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
* Copyright (C) Octavo Systems 2021 - All Rights Reserved
* Author: Neeraj Dantu <dantuguf14105@gmail.com> for Octavo Systems
*/
/dts-v1/;
#include "stm32mp157c-osd32mp1-red.dtsi"
#include "stm32mp157cac-pinctrl.dtsi"
#include "stm32mp157c-m4-srm.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include "stm32mp157.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include "stm32mp15-m4-srm.dtsi"
#include <dt-bindings/mfd/st,stpmic1.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/rtc/rtc-stm32.h>
/ {
model = "Octavo OSD32MP1-RED board";
compatible = "octavo,osd32mp1-red", "st,stm32mp157";
model = "Octavo OSD32MP1 RED board";
compatible = "octavo,stm32mp157c-osd32mp1-red", "st,stm32mp157";
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
};
@ -32,26 +29,20 @@
reset-gpios = <&gpiog 5 GPIO_ACTIVE_LOW>;
};
clocks {
clk_ext_camera: clk-ext-camera {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
retram: retram@0x38000000 {
compatible = "shared-dma-pool";
reg = <0x38000000 0x10000>;
no-map;
};
mcuram: mcuram@0x30000000 {
compatible = "shared-dma-pool";
reg = <0x30000000 0x40000>;
no-map;
};
mcuram2: mcuram2@0x10000000 {
mcuram2:mcuram2@10000000{
compatible = "shared-dma-pool";
reg = <0x10000000 0x40000>;
no-map;
@ -59,22 +50,33 @@
vdev0vring0:vdev0vring0@10040000{
compatible = "shared-dma-pool";
reg = <0x10040000 0x2000>;
reg = <0x10040000 0x1000>;
no-map;
};
vdev0vring1: vdev0vring1@10042000 {
vdev0vring1:vdev0vring1@10041000{
compatible = "shared-dma-pool";
reg = <0x10042000 0x2000>;
reg = <0x10041000 0x1000>;
no-map;
};
vdev0buffer: vdev0buffer@10044000 {
vdev0buffer:vdev0buffer@10042000{
compatible = "shared-dma-pool";
reg = <0x10044000 0x4000>;
reg = <0x10042000 0x4000>;
no-map;
};
mcuram:mcuram@30000000{
compatible = "shared-dma-pool";
reg = <0x30000000 0x40000>;
no-map;
};
retram:retram@38000000{
compatible = "shared-dma-pool";
reg = <0x38000000 0x10000>;
no-map;
};
gpu_reserved:gpu@d4000000{
reg = <0xd4000000 0x4000000>;
@ -95,19 +97,6 @@
stdout-path = "serial0:115200n8";
};
sram: sram@10050000 {
compatible = "mmio-sram";
reg = <0x10050000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10050000 0x10000>;
dma_pool: dma_pool@0 {
reg = <0x0 0x10000>;
pool;
};
};
led {
compatible = "gpio-leds";
blue {
@ -116,18 +105,6 @@
linux,default-trigger = "heartbeat";
default-state = "off";
};
};
sound {
compatible = "audio-graph-card";
label = "STM32MP1-DK";
routing =
"Playback" , "MCLK",
"Capture" , "MCLK",
"MICL" , "Mic Bias";
dais = <&i2s2_port>;
status = "okay";
};
usb_phy_tuning:usb-phy-tuning{
@ -141,43 +118,24 @@
st,no-lsfs-sc;
};
clocks {
clk_ext_camera: clk-ext-camera {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
vin:vin{
compatible = "regulator-fixed";
regulator-name = "vin";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
clk_lsi: clk-lsi {
clock-frequency = <32000>;
};
clk_hsi: clk-hsi {
clock-frequency = <64000000>;
};
clk_csi: clk-csi {
clock-frequency = <4000000>;
};
clk_lse: clk-lse {
clock-frequency = <32768>;
};
clk_hse: clk-hse {
clock-frequency = <24000000>;
sound {
compatible = "audio-graph-card";
label = "STM32MP15-DK";
dais = <&i2s2_port>;
status = "okay";
};
};
}; /*root*/
&pinctrl {
u-boot,dm-pre-reloc;
dcmi_pins_mx: dcmi_mx-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
@ -363,11 +321,16 @@
<STM32_PINMUX('I', 0, AF14)>, /* LTDC_G5 */
<STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
<STM32_PINMUX('I', 2, AF14)>, /* LTDC_G7 */
<STM32_PINMUX('G', 7, AF14)>, /* LTDC_CLK */
<STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
<STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LTDC_CLK */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
};
@ -423,7 +386,7 @@
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
bias-disable;
drive-push-pull;
slew-rate = <3>;
slew-rate = <2>;
};
};
@ -444,7 +407,7 @@
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
bias-disable;
drive-push-pull;
slew-rate = <3>;
slew-rate = <2>;
};
pins3 {
u-boot,dm-pre-reloc;
@ -680,18 +643,6 @@
};
};
usart2_idle_pins_mx: usart2_sleep_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
<STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
bias-disable;
};
};
usart2_sleep_pins_mx: usart2_sleep_mx-0 {
pins {
pinmux = <STM32_PINMUX('D', 3, ANALOG)>, /* USART2_CTS */
@ -701,6 +652,28 @@
};
};
cec_pins_mx: cec-1 {
pins {
pinmux = <STM32_PINMUX('B', 6, AF5)>;
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
cec_sleep_pins_mx: cec-sleep-1 {
pins {
pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
};
};
stusb1600_pins_mx: stusb1600-0 {
pins {
pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
bias-pull-up;
};
};
m_can1_pins_mx: m_can1_sleep_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */
@ -721,15 +694,6 @@
};
};
stusb1600_pins_mx: stusb1600_mx-0 {
pins {
pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
bias-pull-up;
};
};
};
&pinctrl_z {
@ -770,7 +734,6 @@
<STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
};
};
};
&m4_rproc{
@ -780,25 +743,16 @@
mbox-names = "vq0", "vq1", "shutdown";
interrupt-parent = <&exti>;
interrupts = <68 1>;
interrupt-names = "wdg";
wakeup-source;
recovery;
status = "okay";
};
&bsec{
status = "okay";
};
&dcmi{
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dcmi_pins_mx>;
pinctrl-1 = <&dcmi_sleep_pins_mx>;
status = "okay";
port {
dcmi_0: endpoint {
remote-endpoint = <&ov5640_0>;
@ -809,20 +763,12 @@
pclk-max-frequency = <77000000>;
};
};
};
&dsi{
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
@ -838,7 +784,7 @@
};
};
panel@0 {
panel_otm8009a: panel-otm8009a@0 {
compatible = "orisetech,otm8009a";
reg = <0>;
reset-gpios = <&gpioe 9 GPIO_ACTIVE_LOW>;
@ -851,8 +797,6 @@
};
};
};
};
&ethernet0{
@ -862,10 +806,12 @@
status = "okay";
st,eth_clk_sel = <1>;
st,eth-clk-sel; //custom
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
nvmem-cells = <&ethernet_mac_address>;
nvmem-cell-names = "mac-address";
mdio0 {
#address-cells = <1>;
@ -875,20 +821,24 @@
reg = <3>;
};
};
};
&gpu{
status = "okay";
contiguous-area = <&gpu_reserved>;
};
&hash1 {
status = "okay";
};
&hsem{
status = "okay";
};
&cryp1{
u-boot,dm-pre-reloc;
status = "okay";
};
&i2c1{
@ -896,16 +846,11 @@
pinctrl-0 = <&i2c1_pins_mx>;
pinctrl-1 = <&i2c1_sleep_pins_mx>;
status = "okay";
i2c-scl-rising-time-ns = <100>;
i2c-scl-falling-time-ns = <7>;
/delete-property/dmas;
/delete-property/dma-names;
touchscreen@2a {
compatible = "focaltech,ft6236";
reg = <0x2a>;
@ -914,29 +859,31 @@
interrupt-controller;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
panel = <&panel_otm8009a>;
vcc-supply = <&v3v3>;
status = "okay";
};
touchscreen@38 {
compatible = "focaltech,ft6336";
compatible = "focaltech,ft6236";
reg = <0x38>;
interrupts = <2 2>;
interrupt-parent = <&gpiof>;
interrupt-controller;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
panel = <&panel_otm8009a>;
vcc-supply = <&v3v3>;
status = "okay";
};
hdmi-transmitter@39 {
compatible = "sil,sii9022";
reg = <0x39>;
reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpiog>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ltdc_pins_mx>;
pinctrl-1 = <&ltdc_sleep_pins_mx>;
#sound-dai-cells = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -948,15 +895,14 @@
};
};
port@1 {
reg = <1>;
port@3 {
reg = <3>;
sii9022_tx_endpoint: endpoint {
remote-endpoint = <&i2s2_endpoint>;
};
};
};
};
};
&i2c2{
@ -964,10 +910,8 @@
pinctrl-0 = <&i2c2_pins_mx &i2c2_pins_z_mx>;
pinctrl-1 = <&i2c2_sleep_pins_mx &i2c2_sleep_pins_z_mx>;
status = "okay";
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
/delete-property/dmas;
/delete-property/dma-names;
@ -977,6 +921,10 @@
clocks = <&clk_ext_camera>;
clock-names = "xclk";
DOVDD-supply = <&v3v3>;
//powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
//reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
//powerdown-gpios = <&gpioc 3 GPIO_ACTIVE_HIGH>; //custom
//reset-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; //custom
rotation = <180>;
status = "okay";
@ -992,7 +940,6 @@
};
};
};
};
&i2c4{
@ -1001,10 +948,9 @@
pinctrl-0 = <&i2c4_pins_z_mx>;
pinctrl-1 = <&i2c4_sleep_pins_z_mx>;
status = "okay";
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
clock-frequency = <400000>;
/delete-property/ dmas;
/delete-property/ dma-names;
@ -1016,12 +962,19 @@
pinctrl-0 = <&stusb1600_pins_mx>;
pinctrl-names = "default";
status = "okay";
vdd-supply = <&vin>;
typec_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
power-opmode = "default";
port {
con_usbotg_hs_ep: endpoint {
remote-endpoint = <&usbotg_hs_ep>;
};
};
};
};
@ -1039,13 +992,22 @@
regulators{
compatible = "st,stpmic1-regulators";
buck1-supply = <&vin>;
buck2-supply = <&vin>;
buck3-supply = <&vin>;
buck4-supply = <&vin>;
ldo1-supply = <&v3v3>;
ldo2-supply = <&vin>;
ldo3-supply = <&vdd_ddr>;
ldo4-supply = <&vin>;
ldo5-supply = <&vin>;
ldo6-supply = <&v3v3>;
vref_ddr-supply = <&vin>;
boost-supply = <&vin>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;
vddcore:buck1{
regulator-name = "vddcore";
regulator-min-microvolt = <1200000>;
@ -1083,22 +1045,20 @@
regulator-initial-mode = <0>;
};
v1v8_ldo1: ldo1 {
regulator-name = "v1v8_ldo1";
v1v8_audio:ldo1{
regulator-name = "v1v8_audio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
interrupts = <IT_CURLIM_LDO1 0>;
};
v2v8_ldo2: ldo2 { //custom
regulator-name = "v2v8_ldo2";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
v3v3_hdmi:ldo2{
regulator-name = "v3v3_hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
interrupts = <IT_CURLIM_LDO2 0>;
};
vtt_ddr:ldo3{
@ -1111,8 +1071,6 @@
vdd_usb:ldo4{
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
};
@ -1126,11 +1084,10 @@
v3v3_dsi:ldo6{
regulator-name = "v3v3_dsi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
interrupts = <IT_CURLIM_LDO6 0>;
};
vref_ddr:vref_ddr{
@ -1155,15 +1112,16 @@
vbus_sw:pwr_sw2{
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
regulator-active-discharge;
regulator-active-discharge = <1>;
regulator-always-on;
};
};
onkey{
compatible = "st,stpmic1-onkey";
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
interrupt-names = "onkey-falling", "onkey-rising";
power-off-time-sec = <10>;
status = "okay";
};
@ -1172,6 +1130,11 @@
status = "disabled";
};
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c5{
@ -1185,6 +1148,20 @@
};
&spi5 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi5_pins_mx>;
pinctrl-1 = <&spi5_sleep_pins_mx>;
cs-gpios = <&gpiof 6 0>;
status = "okay";
spidev: spidev@0 {
compatible = "rohm,dh2228fv";
spi-max-frequency = <30000000>;
reg = <0>;
};
};
&i2s2{
clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
clock-names = "pclk", "i2sclk", "x8k", "x11k";
@ -1200,30 +1177,23 @@
mclk-fs = <256>;
};
};
};
&ipcc{
status = "okay";
};
&iwdg2{
status = "okay";
timeout-sec = <32>;
};
&ltdc{
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ltdc_pins_mx>;
pinctrl-1 = <&ltdc_sleep_pins_mx>;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
ltdc_ep0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&sii9022_in>;
@ -1233,36 +1203,48 @@
reg = <1>;
remote-endpoint = <&dsi_in>;
};
};
};
};
&pwr{
status = "okay";
pwr-regulators {
&pwr_regulators {
vdd-supply = <&vdd>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
};
&rcc{
u-boot,dm-pre-reloc;
status = "okay";
};
&rng1{
status = "okay";
};
&rtc{
status = "okay";
st,lsco = <RTC_OUT2_RMP>;
};
&cec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cec_pins_mx>;
pinctrl-1 = <&cec_sleep_pins_mx>;
status = "okay";
};
&cpu0{
cpu-supply = <&vddcore>;
};
&cpu1{
cpu-supply = <&vddcore>;
};
&crc1 {
status = "okay";
};
&dts {
status = "okay";
};
&sdmmc1{
@ -1272,11 +1254,12 @@
pinctrl-1 = <&sdmmc1_opendrain_pins_mx>;
pinctrl-2 = <&sdmmc1_sleep_pins_mx>;
status = "okay";
broken-cd;
cd-gpios = <&gpioe 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
};
&sdmmc2{
@ -1294,18 +1277,13 @@
vmmc-supply = <&v3v3>;
vqmmc-supply = <&v3v3>;
mmc-ddr-3_3v;
};
&sdmmc3{
u-boot,dm-pre-reloc;
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc3_pins_mx>;
pinctrl-1 = <&sdmmc3_opendrain_pins_mx>;
pinctrl-2 = <&sdmmc3_sleep_pins_mx>;
status = "okay";
arm,primecell-periphid = <0x10153180>;
non-removable;
st,neg-edge;
@ -1320,14 +1298,11 @@
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
status = "okay";
};
};
&tamp{
status = "okay";
};
&timers5 {
@ -1350,29 +1325,32 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart4_pins_mx>;
pinctrl-1 = <&uart4_sleep_pins_mx>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&usart2{
pinctrl-names = "default", "sleep", "idle";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&usart2_pins_mx>;
pinctrl-1 = <&usart2_sleep_pins_mx>;
pinctrl-2 = <&usart2_idle_pins_mx>;
st,hw-flow-ctrl;
uart-has-rtscts;
status = "okay";
bluetooth {
shutdown-gpios = <&gpioe 10 GPIO_ACTIVE_HIGH>;
compatible = "brcm,bcm43438-bt";
max-speed = <3000000>;
vbat-supply = <&v3v3>;
vddio-supply = <&v3v3>;
};
};
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
<&vdev0vring1>, <&vdev0buffer>;
&sram {
dma_pool: dma_pool@0 {
reg = <0x50000 0x10000>;
pool;
};
};
&dma1 {
@ -1383,6 +1361,37 @@ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
sram = <&dma_pool>;
};
&adc {
vdd-supply = <&vdd>;
vdda-supply = <&v3v3_eth>;
vref-supply = <&v3v3_eth>;
status = "okay";
adc1: adc@0 {
st,min-sample-time-nsecs = <5000>;
st,adc-channels = <0 1>;
status = "okay";
};
adc_temp: temp {
status = "okay";
};
};
// WARNING: Do not try to enable DAC1 and DCMI
// This devices share the same pin PA4
/* &dac {
pinctrl-names = "default";
status = "okay";
dac1: dac@1 {
pinctrl-0 = <&dac_ch1_pins_a>;
status = "disabled";
};
dac2: dac@2 {
pinctrl-0 = <&dac_ch2_pins_a>;
status = "okay";
};
};*/
&usbh_ehci {
phys = <&usbphyc_port0>;
@ -1397,70 +1406,32 @@ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
};
&usbotg_hs {
extcon = <&typec>;
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
usb-role-switch;
status = "okay";
port {
usbotg_hs_ep: endpoint {
remote-endpoint = <&con_usbotg_hs_ep>;
};
};
};
&usbphyc {
vdd3v3-supply = <&vdd_usb>;
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
st,phy-tuning = <&usb_phy_tuning>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
st,phy-tuning = <&usb_phy_tuning>;
};
&spi5 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi5_pins_mx>;
pinctrl-1 = <&spi5_sleep_pins_mx>;
cs-gpios = <&gpiof 6 0>;
status = "okay";
spidev: spidev@0 {
compatible = "rohm,dh2228fv";
spi-max-frequency = <30000000>;
reg = <0>;
};
};
// WARNING: Do not try to enable DAC1 and DCMI
// This devices share the same pin PA4
&dac {
pinctrl-names = "default";
vref-supply = <&vrefbuf>;
status = "okay";
dac1: dac@1 {
pinctrl-0 = <&dac_ch1_pins_a>;
status = "disabled";
};
dac2: dac@2 {
pinctrl-0 = <&dac_ch2_pins_a>;
status = "okay";
};
};
&adc {
vdd-supply = <&vdd>;
vdda-supply = <&vdd>;
vref-supply = <&v3v3_eth>;
status = "okay";
adc1: adc@0 {
st,adc-channels = <0 1>; //ANA0 ANA1
status = "okay";
};
adc2: adc@100 {
//st,adc-channels = <0 1 2 6 12 18 19>;
status = "okay";
};
};
&m_can1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&m_can1_pins_mx>;

2077
board/octavo/osd32mp1-red/linux-dts/stm32mp157c-osd32mp1-red.dtsi
View File

File diff suppressed because it is too large Load Diff

2
board/octavo/osd32mp1-red/overlay/boot/extlinux/extlinux.conf
View File

@ -1,4 +1,4 @@
label osd32mp1-red-buildroot
kernel /boot/zImage
devicetree /boot/osd32mp1-red.dtb
devicetree /boot/stm32mp157c-osd32mp1-red.dtb
append root=/dev/mmcblk1p4 rootwait

1124
board/octavo/osd32mp1-red/patches/uboot/0001-Add-OSD32MP1-RED-Device-Tree-support.patch
View File

File diff suppressed because it is too large Load Diff

47
board/octavo/osd32mp1-red/patches/uboot/0002-configs-stm32mp15_trusted_defconfig-disable-environm.patch
View File

@ -1,32 +1,49 @@
From 3feee3e00dcb9467b5345671300e7c73f3e05f93 Mon Sep 17 00:00:00 2001
From 27a516e2ad464bf1de5e23e8277e0f6d6735bd21 Mon Sep 17 00:00:00 2001
From: Kory Maincent <kory.maincent@bootlin.com>
Date: Tue, 5 Oct 2021 14:31:28 +0200
Date: Mon, 3 Oct 2022 12:20:40 +0200
Subject: [PATCH 2/2] configs/stm32mp15_trusted_defconfig: disable environment
select only ENV_IS_NOWHERE
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
---
configs/stm32mp15_trusted_defconfig | 6 ------
1 file changed, 6 deletions(-)
board/st/stm32mp1/stm32mp1.c | 4 ++++
configs/stm32mp15_trusted_defconfig | 9 ---------
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 48591b2f1e..ba510d843c 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -78,6 +78,10 @@ DECLARE_GLOBAL_DATA_PTR;
#define USB_START_LOW_THRESHOLD_UV 1230000
#define USB_START_HIGH_THRESHOLD_UV 2150000
+#ifndef CONFIG_SYS_MMC_ENV_DEV
+#define CONFIG_SYS_MMC_ENV_DEV -1
+#endif
+
int board_early_init_f(void)
{
/* nothing to do, only used in SPL */
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 7635d7f6c7..6ec4bcd080 100644
index 2161ccbefa..fd3fed8fb0 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -38,12 +38,6 @@ CONFIG_CMD_MTDPARTS=y
@@ -45,15 +45,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_ENV_IS_NOWHERE=y
-CONFIG_ENV_IS_IN_EXT4=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_IS_IN_UBI=y
-CONFIG_ENV_EXT4_INTERFACE="mmc"
-CONFIG_ENV_EXT4_DEVICE_AND_PART="0:auto"
-CONFIG_ENV_EXT4_FILE="/uboot.env"
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_UBI_PART="UBI"
-CONFIG_ENV_UBI_VOLUME="uboot_config"
-CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_DEV=-1
CONFIG_STM32_ADC=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
CONFIG_CLK_SCMI=y
CONFIG_SET_DFU_ALT_INFO=y
--
2.25.1

12
board/octavo/osd32mp1-red/tfa-dts/stm32mp15-osd32mp1-ddr3-1x4Gb-1066-binG.dtsi → board/octavo/osd32mp1-red/tfa-dts/osd32mp1_ddr_1x4Gb.dtsi
View File

@ -14,7 +14,7 @@
* Relaxed Timing Mode: false
* Address mapping type: RBC
*
* Save Date: 2020.02.08, save Time: 23:22:33
* Save Date: 2020.08.27, save Time: 15:22:11
*/
#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz"
@ -103,12 +103,12 @@
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX0DQTR 0x00112121
#define DDR_DX0DQSTR 0x3D200000
#define DDR_DX1GCR 0x0000CE81
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX1DQTR 0x11100121
#define DDR_DX1DQSTR 0x3D200000
#define DDR_DX2GCR 0x0000CE80
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
@ -117,3 +117,5 @@
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"

6
board/octavo/osd32mp1-red/tfa-dts/stm32mp157c-osd32mp1-red-fw-config.dts Normal file
View File

@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (c) 2020, STMicroelectronics - All Rights Reserved
*/
#include "stm32mp15-ddr-512m-fw-config.dts"

606
board/octavo/osd32mp1-red/tfa-dts/osd32mp1-red.dts → board/octavo/osd32mp1-red/tfa-dts/stm32mp157c-osd32mp1-red.dts
View File

@ -4,300 +4,100 @@
* Author: STM32CubeMX code generation for STMicroelectronics.
*/
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
/dts-v1/;
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-osd32mp1-ddr3-1x4Gb-1066-binG.dtsi"
#include "stm32mp157c.dtsi"
#include "stm32mp157cac-pinctrl.dtsi"
#include "stm32mp15-ddr.dtsi"
#include "stm32mp157c-security.dtsi"
#include <dt-bindings/soc/st,stm32-etzpc.h>
#include <dt-bindings/power/stm32mp1-power.h>
#include "stm32mp157.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include "osd32mp1_ddr_1x4Gb.dtsi"
/ {
model = "Octavo OSD32MP1-RED board";
compatible = "octavo,osd32mp1-red", "st,stm32mp157";
model = "Octavo OSD32MP1 RED board";
compatible = "octavo,stm32mp157c-osd32mp1-red", "st,stm32mp157";
aliases {
serial0 = &uart4;
};
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
};
vin: vin {
compatible = "regulator-fixed";
regulator-name = "vin";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio25 = &gpioz;
i2c3 = &i2c4;
};
clocks {
clk_lse: clk-lse {
st,drive = < LSEDRV_MEDIUM_HIGH >;
};
clk_hse: clk-hse {
st,digbypass;
};
};
}; /*root*/
&pinctrl {
sdmmc1_pins_mx: sdmmc1_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
};
sdmmc2_pins_mx: sdmmc2_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
<STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
<STM32_PINMUX('C', 7, AF10)>, /* SDMMC2_D7 */
<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
bias-pull-up;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
bias-pull-up;
drive-push-pull;
slew-rate = <2>;
};
};
sdmmc3_pins_mx: sdmmc3_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
<STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
<STM32_PINMUX('F', 1, AF9)>, /* SDMMC3_CMD */
<STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
<STM32_PINMUX('F', 5, AF9)>; /* SDMMC3_D2 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
uart4_pins_mx: uart4_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
};
};
&pinctrl_z {
i2c4_pins_z_mx: i2c4_mx-0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
};
&rcc {
st,csi-cal;
st,hsi-cal;
st,cal-sec = <60>;
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
0 /*MCU*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;
st,pkcs = <
CLK_CKPER_HSE
CLK_ETH_PLL3Q
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_DISABLED
CLK_SPI2S23_PLL3Q
CLK_SPI45_PCLK2
CLK_SPI6_DISABLED
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_DISABLED
CLK_I2C12_HSI
CLK_I2C35_PCLK1
CLK_UART1_DISABLED
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_DISABLED
CLK_UART78_DISABLED
CLK_SPDIF_DISABLED
CLK_SAI1_DISABLED
CLK_SAI2_CKPER
CLK_SAI3_DISABLED
CLK_SAI4_DISABLED
CLK_RNG1_LSI
CLK_LPTIM1_DISABLED
CLK_LPTIM23_DISABLED
CLK_LPTIM45_DISABLED
>;
pll1:st,pll@0 {
cfg = < 2 80 0 1 1 PQR(1,0,0) >;
frac = < 0x800>;
};
pll2:st,pll@1 {
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400>;
};
pll3:st,pll@2 {
cfg = < 1 61 3 5 36 PQR(1,1,0) >;
frac = < 0x1000 >;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
};
};
&bsec {
status = "okay";
secure-status = "okay";
board_id: board_id@ec {
reg = <0xec 0x4>;
status = "okay";
secure-status = "okay";
st,non-secure-otp;
};
};
&clk_hse {
st,digbypass;
};
&cpu0 {
cpu-supply = <&vddcore>;
};
&cpu1 {
cpu-supply = <&vddcore>;
};
&hash1 {
status = "okay";
};
&cryp1 {
status = "okay";
};
&etzpc {
st,decprot = <
/*"Non Secured" peripherals*/
DECPROT(STM32MP1_ETZPC_DCMI_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SPI6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SPI2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SAI2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SDMMC3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_DLYBSD3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SPI5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_TIM5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_UART4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_USART2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
/*Restriction: following IDs are not managed - please to use User-Section if needed:
STM32MP1_ETZPC_DMA1_ID, STM32MP1_ETZPC_DMA2_ID, STM32MP1_ETZPC_DMAMUX_ID,
STM32MP1_ETZPC_SRAMx_ID, STM32MP1_ETZPC_RETRAM_ID, STM32MP1_ETZPC_BKPSRAM_ID*/
/*STM32CubeMX generates a basic and standard configuration for ETZPC.
Additional device configurations can be added here if needed.
"etzpc" node could be also overloaded in "addons" User-Section.*/
DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_LOCK)
DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_LOCK)
DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_LOCK)
>;
secure-status = "okay";
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_z_mx>;
status = "okay";
secure-status = "okay";
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
clock-frequency = <400000>;
status = "okay";
secure-status = "okay";
pmic: stpmic@33 {
compatible = "st,stpmic1";
@ -306,17 +106,24 @@
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
st,main-control-register = <0x04>;
st,vin-control-register = <0xc0>;
st,usb-control-register = <0x20>;
secure-status = "okay";
regulators {
compatible = "st,stpmic1-regulators";
buck1-supply = <&vin>;
buck2-supply = <&vin>;
buck3-supply = <&vin>;
buck4-supply = <&vin>;
ldo1-supply = <&v3v3>;
ldo2-supply = <&vin>;
ldo3-supply = <&vdd_ddr>;
ldo4-supply = <&vin>;
ldo5-supply = <&vin>;
ldo6-supply = <&v3v3>;
vref_ddr-supply = <&vin>;
boost-supply = <&vin>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;
vddcore: buck1 {
regulator-name = "vddcore";
@ -398,7 +205,7 @@
};
};
v1v8_audio: ldo1 {
v1v8_ldo1: ldo1 {
regulator-name = "v1v8_audio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -411,7 +218,7 @@
};
};
v3v3_hdmi: ldo2 {
v3v3_ldo2: ldo2 {
regulator-name = "v3v3_hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -445,8 +252,9 @@
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
standby-ddr-sr{
regulator-off-in-suspend;
regulator-on-in-suspend;
};
standby-ddr-off{
regulator-off-in-suspend;
@ -466,8 +274,8 @@
};
};
v1v2_hdmi: ldo6 {
regulator-name = "v1v2_hdmi";
v1v2_ldo6: ldo6 {
regulator-name = "v1v2_ldo6";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
@ -493,123 +301,271 @@
regulator-off-in-suspend;
};
};
};
bst_out: boost {
regulator-name = "bst_out";
};
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
regulator-active-discharge = <1>;
};
};
};
};
&iwdg2 {
timeout-sec = <32>;
secure-timeout-sec = <5>;
status = "okay";
secure-status = "okay";
timeout-sec = <32>;
};
&pwr{
status = "okay";
secure-status = "okay";
&nvmem_layout {
nvmem-cells = <&cfg0_otp>,
<&part_number_otp>,
<&monotonic_otp>,
<&nand_otp>,
<&uid_otp>,
<&package_otp>,
<&hw2_otp>,
<&pkh_otp>,
<&board_id>;
nvmem-cell-names = "cfg0_otp",
"part_number_otp",
"monotonic_otp",
"nand_otp",
"uid_otp",
"package_otp",
"hw2_otp",
"pkh_otp",
"board_id";
};
&pwr_regulators {
system_suspend_supported_soc_modes = <
STM32_PM_CSLEEP_RUN
STM32_PM_CSTOP_ALLOW_LP_STOP
STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR
>;
system_off_soc_mode = <STM32_PM_CSTOP_ALLOW_STANDBY_DDR_OFF>;
pwr-regulators {
vdd-supply = <&vdd>;
};
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&rcc {
status = "okay";
secure-status = "okay";
st,hsi-cal;
st,csi-cal;
st,cal-sec = <60>;
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
0 /*MCU*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;
st,pkcs = <
CLK_CKPER_HSE
CLK_ETH_PLL3Q
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_CKPER
CLK_SPI45_PCLK2
CLK_SPI6_DISABLED
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_DISABLED
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_DISABLED
CLK_UART78_DISABLED
CLK_SPDIF_DISABLED
CLK_SAI1_DISABLED
CLK_SAI2_DISABLED
CLK_SAI3_DISABLED
CLK_SAI4_DISABLED
CLK_RNG1_LSI
CLK_LPTIM1_DISABLED
CLK_LPTIM23_DISABLED
CLK_LPTIM45_DISABLED
>;
pll1:st,pll@0 {
cfg = < 2 80 0 1 1 PQR(1,0,0) >;
frac = < 0x800>;
};
pll2:st,pll@1 {
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400>;
};
pll3:st,pll@2 {
cfg = < 1 61 3 5 36 PQR(1,1,0) >;
frac = < 0x1000 >;
};
pll4: st,pll@3 {
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
};
};
&rng1 {
status = "okay";
secure-status = "okay";
};
&rtc {
status = "okay";
secure-status = "okay";
};
&sdmmc1 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_pins_mx>;
status = "okay";
broken-cd;
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
status = "okay";
};
&sdmmc2{
pinctrl-names = "default";
pinctrl-0 = <&sdmmc2_pins_mx>;
status = "okay";
};
&sdmmc3{
pinctrl-names = "default";
pinctrl-0 = <&sdmmc3_pins_mx>;
status = "okay";
};
&tamp{
status = "okay";
&timers15 {
secure-status = "okay";
st,hsi-cal-input = <7>;
st,csi-cal-input = <8>;
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_mx>;
status = "okay";
};
&usbotg_hs {
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
usb-role-switch;
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};
/delete-node/ &qspi_bk1_pins_a;
/delete-node/ &qspi_bk2_pins_a;
/delete-node/ &qspi_clk_pins_a;
/delete-node/ &sdmmc1_b4_pins_a;
/delete-node/ &sdmmc1_dir_pins_a;
/delete-node/ &sdmmc1_dir_pins_b;
/delete-node/ &sdmmc2_b4_pins_a;
/delete-node/ &sdmmc2_d47_pins_a;
/delete-node/ &uart4_pins_a;
/delete-node/ &uart7_pins_a;
/delete-node/ &usart3_pins_a;
/delete-node/ &usart3_pins_b;
/delete-node/ &i2c4_pins_a;
&pinctrl {
sdmmc1_pins_mx: sdmmc1-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
slew-rate = <2>;
drive-push-pull;
bias-disable;
};
};
sdmmc2_pins_mx: sdmmc2_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
<STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
<STM32_PINMUX('C', 7, AF10)>, /* SDMMC2_D7 */
<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
bias-pull-up;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
bias-pull-up;
drive-push-pull;
slew-rate = <2>;
};
};
uart4_pins_mx: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
};
&pinctrl_z {
i2c4_pins_z_mx: i2c4-0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
};

24
configs/octavo_osd32mp1_red_defconfig
View File

@ -5,8 +5,8 @@ BR2_cortex_a7=y
# global patch directory
BR2_GLOBAL_PATCH_DIR="board/octavo/osd32mp1-red/patches"
# Linux headers same as kernel, a 4.19 series
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_19=y
# Linux headers same as kernel, a 5.10 series
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_10=y
# rootfs overlay
BR2_ROOTFS_OVERLAY="board/octavo/osd32mp1-red/overlay/"
@ -20,11 +20,11 @@ BR2_ROOTFS_POST_SCRIPT_ARGS="-c board/octavo/osd32mp1-red/genimage.cfg"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_GIT=y
BR2_LINUX_KERNEL_CUSTOM_REPO_URL="https://github.com/STMicroelectronics/linux.git"
BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="v4.19-stm32mp-r3.3"
BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="v5.10-stm32mp-r2.1"
BR2_LINUX_KERNEL_DEFCONFIG="multi_v7"
BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(LINUX_DIR)/arch/arm/configs/fragment-01-multiv7_cleanup.config $(LINUX_DIR)/arch/arm/configs/fragment-02-multiv7_addons.config"
BR2_LINUX_KERNEL_DTS_SUPPORT=y
BR2_LINUX_KERNEL_INTREE_DTS_NAME="osd32mp1-red"
BR2_LINUX_KERNEL_INTREE_DTS_NAME="stm32mp157c-osd32mp1-red"
BR2_LINUX_KERNEL_CUSTOM_DTS_PATH="board/octavo/osd32mp1-red/linux-dts/*"
BR2_LINUX_KERNEL_INSTALL_TARGET=y
BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
@ -38,11 +38,14 @@ BR2_TARGET_ROOTFS_EXT2_4=y
BR2_TARGET_ARM_TRUSTED_FIRMWARE=y
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_GIT=y
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_REPO_URL="https://github.com/STMicroelectronics/arm-trusted-firmware.git"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_REPO_VERSION="v2.0-stm32mp-r1.5"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_REPO_VERSION="v2.4-stm32mp-r1"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="stm32mp1"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_DTS_PATH="board/octavo/osd32mp1-red/tfa-dts/*"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_ADDITIONAL_VARIABLES="STM32MP_SDMMC=1 AARCH32_SP=sp_min DTB_FILE_NAME=osd32mp1-red.dtb STM32MP_USB_PROGRAMMER=1 CFLAGS=-Wno-array-bounds"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_IMAGES="*.stm32"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_FIP=y
BR2_TARGET_ARM_TRUSTED_FIRMWARE_UBOOT_AS_BL33=y
BR2_TARGET_ARM_TRUSTED_FIRMWARE_UBOOT_BL33_IMAGE="u-boot-nodtb.bin"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_ADDITIONAL_VARIABLES="STM32MP_SDMMC=1 AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-osd32mp1-red.dtb STM32MP_USB_PROGRAMMER=1 BL33_CFG=$(BINARIES_DIR)/u-boot.dtb"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_IMAGES="*.stm32 fip.bin"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_NEEDS_DTC=y
# U-Boot
@ -50,11 +53,12 @@ BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
BR2_TARGET_UBOOT_CUSTOM_GIT=y
BR2_TARGET_UBOOT_CUSTOM_REPO_URL="https://github.com/STMicroelectronics/u-boot.git"
BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="v2018.11-stm32mp-r3.2"
BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="v2020.10-stm32mp-r2.1"
BR2_TARGET_UBOOT_BOARD_DEFCONFIG="stm32mp15_trusted"
# BR2_TARGET_UBOOT_FORMAT_BIN is not set
BR2_TARGET_UBOOT_FORMAT_STM32=y
BR2_TARGET_UBOOT_CUSTOM_MAKEOPTS="DEVICE_TREE=osd32mp1-red"
BR2_TARGET_UBOOT_FORMAT_CUSTOM=y
BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot-nodtb.bin u-boot.dtb"
BR2_TARGET_UBOOT_CUSTOM_MAKEOPTS="DEVICE_TREE=stm32mp157c-osd32mp1-red"
# Package needed to generate the image
BR2_PACKAGE_HOST_GENIMAGE=y