From 81253000885b3eaa2f521a998463c119a1c989ba Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Thu, 5 May 2022 06:54:43 -0600 Subject: [PATCH] configs/zynqmp_zcu106_defconfig: uboot dp pll patch This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-revA evaluation board. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. This patch was build and run tested on a zynqmp-zcu106-revA target board. Upstream-Status: submitted (https://lore.kernel.org/all/62538b4a04dee28a6fc8ac5b85f8c845a5a76aa4.1651740988.git.michal.simek@amd.com/) This patch will be removed from buildroot in a future release when no longer necessary. Signed-off-by: Neal Frager Signed-off-by: Peter Korsgaard --- ...qmp-zcu102-revA-Fix-DP-PLL-configura.patch | 40 +++++++++++++++++++ configs/zynqmp_zcu106_defconfig | 1 + 2 files changed, 41 insertions(+) create mode 100644 board/zynqmp/zcu106/patches/uboot/0001-arm64-zynqmp-zynqmp-zcu102-revA-Fix-DP-PLL-configura.patch diff --git a/board/zynqmp/zcu106/patches/uboot/0001-arm64-zynqmp-zynqmp-zcu102-revA-Fix-DP-PLL-configura.patch b/board/zynqmp/zcu106/patches/uboot/0001-arm64-zynqmp-zynqmp-zcu102-revA-Fix-DP-PLL-configura.patch new file mode 100644 index 0000000000..4281880da0 --- /dev/null +++ b/board/zynqmp/zcu106/patches/uboot/0001-arm64-zynqmp-zynqmp-zcu102-revA-Fix-DP-PLL-configura.patch @@ -0,0 +1,40 @@ +From aaaa10b613165b7790fe1c084de007240b5bd77a Mon Sep 17 00:00:00 2001 +From: Neal Frager +Date: Thu, 5 May 2022 13:34:43 +0100 +Subject: [PATCH 1/1] arm64: zynqmp: zynqmp-zcu102-revA: Fix DP PLL + configuration + +This patch fixes the DP audio and video PLL configurations +for the zynqmp-zcu106-revA evaluation board + +The Linux DP driver expects the DP to be using the following PLL config: + - DP video PLL should use the VPLL (0x0) + - DP audio PLL should use the RPLL (0x3) + +Register 0xFD1A0070 configures the DP video PLL. +Register 0xFD1A0074 configures the DP audio PLL. + +Signed-off-by: Neal Frager +Signed-off-by: Michal Simek +--- + board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c +index 15f0be1a43..cbc436289f 100644 +--- a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c ++++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c +@@ -81,8 +81,8 @@ static unsigned long psu_clock_init_data(void) + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); +- psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U); +- psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U); ++ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); ++ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); +-- +2.17.1 + diff --git a/configs/zynqmp_zcu106_defconfig b/configs/zynqmp_zcu106_defconfig index 27967fc0bd..e1ea27a496 100644 --- a/configs/zynqmp_zcu106_defconfig +++ b/configs/zynqmp_zcu106_defconfig @@ -35,3 +35,4 @@ BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y BR2_PACKAGE_HOST_DOSFSTOOLS=y BR2_PACKAGE_HOST_GENIMAGE=y BR2_PACKAGE_HOST_MTOOLS=y +BR2_GLOBAL_PATCH_DIR="board/zynqmp/zcu106/patches"