configs/zynq_qmtech_defconfig: deprecate board
The zynq_qmtech_defconfig has not been maintained for 3 years, and is now using a very out of date u-boot and Linux kernel. Since there are 4 other zynq7000 defconfigs available in buildroot and Julien no longer has a functional board, drop the defconfig. Signed-off-by: Neal Frager <neal.frager@amd.com> Acked-by: Julien Olivain <ju.o@free.fr> [Peter: reword commit message] Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
This commit is contained in:
Neal Frager
Peter Korsgaard
parent
eadde4d23c
commit
790d554474
@ -76,7 +76,6 @@ board/qemu/microblazebe-mmu/0001-net-xilinx-xemaclite-add-2.00.b-revision.patch
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board/qemu/microblazeel-mmu/0001-net-xilinx-xemaclite-add-2.00.b-revision.patch Upstream
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board/qemu/x86/post-build.sh Shellcheck
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board/qemu/x86_64/post-build.sh Shellcheck
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board/qmtech/zynq/patches/linux/0001-DTS-for-QMTech-Zynq-starter-kit.patch Upstream
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board/radxa/rockpi-n8/post-build.sh Shellcheck
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board/raspberrypi/post-build.sh Shellcheck
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board/raspberrypi/post-image.sh Shellcheck
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@ -1708,14 +1708,12 @@ F: configs/ts7680_defconfig
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F: package/paho-mqtt-c
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N: Julien Olivain <ju.o@free.fr>
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F: board/qmtech/zynq/
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F: board/spike/
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F: board/technexion/imx8mmpico/
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F: board/technexion/imx8mpico/
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F: configs/imx8mmpico_defconfig
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F: configs/imx8mpico_defconfig
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F: configs/spike_riscv64_defconfig
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F: configs/zynq_qmtech_defconfig
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F: package/fluid-soundfont/
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F: package/fluidsynth/
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F: package/glslsandbox-player/
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@ -1,418 +0,0 @@
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From 22d955122ac0f7ac74ab74aadebf6b8edaf0bbbd Mon Sep 17 00:00:00 2001
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From: Julien Olivain <juju@cotds.org>
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Date: Sun, 15 Dec 2019 18:45:40 +0100
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Subject: [PATCH] DTS for QMTech Zynq starter kit
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Signed-off-by: Martin Chabot <martin.chabot@gmail.com>
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Signed-off-by: Julien Olivain <juju@cotds.org>
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---
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arch/arm/boot/dts/zynq-qmtech.dts | 397 ++++++++++++++++++++++++++++++
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1 file changed, 397 insertions(+)
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create mode 100644 arch/arm/boot/dts/zynq-qmtech.dts
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diff --git a/arch/arm/boot/dts/zynq-qmtech.dts b/arch/arm/boot/dts/zynq-qmtech.dts
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new file mode 100644
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index 000000000000..c6081dc0080e
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--- /dev/null
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+++ b/arch/arm/boot/dts/zynq-qmtech.dts
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@@ -0,0 +1,397 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (C) 2011 - 2015 Xilinx
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+ * Copyright (C) 2012 National Instruments Corp.
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+ * Copyright (C) 2019 Martin Chabot <martin.chabot@gmail.com>
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+ */
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+
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+/* Derived from:
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+ * https://github.com/Xilinx/linux-xlnx/blob/xilinx-v2019.2.01/arch/arm/boot/dts/zynq-zc702.dts
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+ */
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+
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+/dts-v1/;
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+#include "zynq-7000.dtsi"
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+
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+/ {
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+ model = "QMTECH XC7Z010 Starter Kit";
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+ compatible = "xlnx,zynq-qmtech", "xlnx,zynq-zc702", "xlnx,zynq-7000";
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+
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+ aliases {
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+ ethernet0 = &gem0;
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+ i2c0 = &i2c0;
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+ serial0 = &uart1;
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+ spi0 = &qspi;
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+ mmc0 = &sdhci0;
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+ };
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+
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+ memory@0 {
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+ device_type = "memory";
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+ reg = <0x0 0x20000000>;
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+ };
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+
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+ chosen {
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+ bootargs = "";
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ ds23 {
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+ label = "ds23";
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+ gpios = <&gpio0 10 0>;
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+ linux,default-trigger = "heartbeat";
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+ };
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+ };
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+
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+};
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+
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+&amba {
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+ ocm: sram@fffc0000 {
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+ compatible = "mmio-sram";
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+ reg = <0xfffc0000 0x10000>;
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+ };
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+};
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+
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+&clkc {
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+ ps-clk-frequency = <33333333>;
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+};
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+
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+&gem0 {
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+ status = "okay";
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+ phy-mode = "rgmii-id";
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+ phy-handle = <ðernet_phy>;
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+
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+ ethernet_phy: ethernet-phy@0 {
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+ reg = <0>;
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+ device_type = "ethernet-phy";
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+ };
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+};
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+
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+&gpio0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_gpio0_default>;
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+};
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+
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+&i2c0 {
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+ status = "disabled";
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+ clock-frequency = <400000>;
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+ pinctrl-names = "default", "gpio";
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+ pinctrl-0 = <&pinctrl_i2c0_default>;
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+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
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+ scl-gpios = <&gpio0 50 0>;
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+ sda-gpios = <&gpio0 51 0>;
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+
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+ i2c-mux@74 {
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+ compatible = "nxp,pca9548";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x74>;
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+
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+ i2c@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+ si570: clock-generator@5d {
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+ #clock-cells = <0>;
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+ compatible = "silabs,si570";
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+ temperature-stability = <50>;
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+ reg = <0x5d>;
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+ factory-fout = <156250000>;
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+ clock-frequency = <148500000>;
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+ };
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+ };
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+
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+ i2c@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+ adv7511: hdmi-tx@39 {
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+ compatible = "adi,adv7511";
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+ reg = <0x39>;
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+ adi,input-depth = <8>;
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+ adi,input-colorspace = "yuv422";
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+ adi,input-clock = "1x";
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+ adi,input-style = <3>;
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+ adi,input-justification = "right";
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+ };
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+ };
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+
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+ i2c@2 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <2>;
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+ eeprom@54 {
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+ compatible = "atmel,24c08";
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+ reg = <0x54>;
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+ };
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+ };
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+
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+ i2c@3 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <3>;
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+ gpio@21 {
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+ compatible = "ti,tca6416";
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+ reg = <0x21>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ };
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+ };
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+
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+ i2c@4 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <4>;
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+ rtc@51 {
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+ compatible = "nxp,pcf8563";
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+ reg = <0x51>;
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+ };
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+ };
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+
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+ i2c@7 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <7>;
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+ hwmon@52 {
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+ compatible = "ti,ucd9248";
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+ reg = <52>;
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+ };
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+ hwmon@53 {
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+ compatible = "ti,ucd9248";
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+ reg = <53>;
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+ };
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+ hwmon@54 {
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+ compatible = "ti,ucd9248";
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+ reg = <54>;
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+ };
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+ };
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+ };
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+};
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+
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+&pinctrl0 {
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+ pinctrl_can0_default: can0-default {
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+ mux {
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+ function = "can0";
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+ groups = "can0_9_grp";
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+ };
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+
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+ conf {
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+ groups = "can0_9_grp";
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+ slew-rate = <0>;
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+ io-standard = <1>;
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+ };
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+
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+ conf-rx {
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+ pins = "MIO46";
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+ bias-high-impedance;
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+ };
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+
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+ conf-tx {
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+ pins = "MIO47";
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+ bias-disable;
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+ };
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+ };
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+
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+ pinctrl_gem0_default: gem0-default {
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+ mux {
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+ function = "ethernet0";
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+ groups = "ethernet0_0_grp";
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+ };
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+
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+ conf {
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+ groups = "ethernet0_0_grp";
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+ slew-rate = <0>;
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+ io-standard = <4>;
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+ };
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+
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+ conf-rx {
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+ pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
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+ bias-high-impedance;
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+ low-power-disable;
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+ };
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+
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+ conf-tx {
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+ pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
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+ bias-disable;
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+ low-power-enable;
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+ };
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+
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+ mux-mdio {
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+ function = "mdio0";
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+ groups = "mdio0_0_grp";
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+ };
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+
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+ conf-mdio {
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+ groups = "mdio0_0_grp";
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+ slew-rate = <0>;
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+ io-standard = <1>;
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+ bias-disable;
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+ };
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+ };
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+
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+ pinctrl_gpio0_default: gpio0-default {
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+ mux {
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+ function = "gpio0";
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+ groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
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+ "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
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+ "gpio0_13_grp", "gpio0_14_grp";
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+ };
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+
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+ conf {
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+ groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
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+ "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
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+ "gpio0_13_grp", "gpio0_14_grp";
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+ slew-rate = <0>;
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+ io-standard = <1>;
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+ };
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+
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+ conf-pull-up {
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+ pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
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+ bias-pull-up;
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+ };
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+
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+ conf-pull-none {
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+ pins = "MIO7", "MIO8";
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+ bias-disable;
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+ };
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+ };
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+
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+ pinctrl_i2c0_default: i2c0-default {
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+ mux {
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+ groups = "i2c0_10_grp";
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+ function = "i2c0";
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+ };
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+
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+ conf {
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+ groups = "i2c0_10_grp";
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+ bias-pull-up;
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+ slew-rate = <0>;
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+ io-standard = <1>;
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+ };
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+ };
|
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+
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+ pinctrl_i2c0_gpio: i2c0-gpio {
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+ mux {
|
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+ groups = "gpio0_50_grp", "gpio0_51_grp";
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+ function = "gpio0";
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+ };
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+
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+ conf {
|
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+ groups = "gpio0_50_grp", "gpio0_51_grp";
|
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+ slew-rate = <0>;
|
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+ io-standard = <1>;
|
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+ };
|
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+ };
|
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+
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+ pinctrl_sdhci0_default: sdhci0-default {
|
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+ mux {
|
||||
+ groups = "sdio0_2_grp";
|
||||
+ function = "sdio0";
|
||||
+ };
|
||||
+
|
||||
+ conf {
|
||||
+ groups = "sdio0_2_grp";
|
||||
+ slew-rate = <0>;
|
||||
+ io-standard = <1>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux-cd {
|
||||
+ groups = "gpio0_0_grp";
|
||||
+ function = "sdio0_cd";
|
||||
+ };
|
||||
+
|
||||
+ conf-cd {
|
||||
+ groups = "gpio0_0_grp";
|
||||
+ bias-high-impedance;
|
||||
+ bias-pull-up;
|
||||
+ slew-rate = <0>;
|
||||
+ io-standard = <1>;
|
||||
+ };
|
||||
+
|
||||
+ mux-wp {
|
||||
+ groups = "gpio0_15_grp";
|
||||
+ function = "sdio0_wp";
|
||||
+ };
|
||||
+
|
||||
+ conf-wp {
|
||||
+ groups = "gpio0_15_grp";
|
||||
+ bias-high-impedance;
|
||||
+ bias-pull-up;
|
||||
+ slew-rate = <0>;
|
||||
+ io-standard = <1>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pinctrl_uart1_default: uart1-default {
|
||||
+ mux {
|
||||
+ groups = "uart1_10_grp";
|
||||
+ function = "uart1";
|
||||
+ };
|
||||
+
|
||||
+ conf {
|
||||
+ groups = "uart1_10_grp";
|
||||
+ slew-rate = <0>;
|
||||
+ io-standard = <1>;
|
||||
+ };
|
||||
+
|
||||
+ conf-rx {
|
||||
+ pins = "MIO25";
|
||||
+ bias-high-impedance;
|
||||
+ };
|
||||
+
|
||||
+ conf-tx {
|
||||
+ pins = "MIO24";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&qspi {
|
||||
+ u-boot,dm-pre-reloc;
|
||||
+ status = "disabled";
|
||||
+ is-dual = <0>;
|
||||
+ num-cs = <1>;
|
||||
+ flash@0 {
|
||||
+ compatible = "n25q128a11";
|
||||
+ reg = <0x0>;
|
||||
+ spi-tx-bus-width = <1>;
|
||||
+ spi-rx-bus-width = <4>;
|
||||
+ spi-max-frequency = <50000000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ partition@qspi-fsbl-uboot {
|
||||
+ label = "qspi-fsbl-uboot";
|
||||
+ reg = <0x0 0x100000>;
|
||||
+ };
|
||||
+ partition@qspi-linux {
|
||||
+ label = "qspi-linux";
|
||||
+ reg = <0x100000 0x500000>;
|
||||
+ };
|
||||
+ partition@qspi-device-tree {
|
||||
+ label = "qspi-device-tree";
|
||||
+ reg = <0x600000 0x20000>;
|
||||
+ };
|
||||
+ partition@qspi-rootfs {
|
||||
+ label = "qspi-rootfs";
|
||||
+ reg = <0x620000 0x5E0000>;
|
||||
+ };
|
||||
+ partition@qspi-bitstream {
|
||||
+ label = "qspi-bitstream";
|
||||
+ reg = <0xC00000 0x400000>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdhci0 {
|
||||
+ u-boot,dm-pre-reloc;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart1 {
|
||||
+ u-boot,dm-pre-reloc;
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
+};
|
||||
--
|
||||
2.23.0
|
||||
|
||||
@ -1,76 +0,0 @@
|
||||
*******************************
|
||||
QMTECH Zynq XC7Z010 Starter Kit
|
||||
*******************************
|
||||
|
||||
This file documents the Buildroot support for the QMTECH [1] Zynq
|
||||
XC7Z010 Starter Kit [2]. It is a low cost (~55$) Zynq based
|
||||
development board. The board user manual is available at
|
||||
[3]. Additional files are available on Github [4].
|
||||
|
||||
|
||||
Build
|
||||
=====
|
||||
|
||||
First, configure Buildroot for the QMTECH Zynq board:
|
||||
|
||||
make zynq_qmtech_defconfig
|
||||
|
||||
Build all components:
|
||||
|
||||
make
|
||||
|
||||
You will find in output/images/ the following files:
|
||||
- boot.bin
|
||||
- boot.vfat
|
||||
- devicetree.dtb
|
||||
- rootfs.cpio
|
||||
- rootfs.cpio.gz
|
||||
- rootfs.cpio.uboot
|
||||
- rootfs.tar
|
||||
- sdcard.img
|
||||
- u-boot.bin
|
||||
- u-boot.img
|
||||
- uImage
|
||||
- zynq-qmtech.dtb
|
||||
|
||||
|
||||
Create a bootable micro SD card
|
||||
===============================
|
||||
|
||||
To determine the device associated to the micro SD card have a look in
|
||||
the /proc/partitions file:
|
||||
|
||||
cat /proc/partitions
|
||||
|
||||
Buildroot prepares a bootable "sdcard.img" image in the output/images/
|
||||
directory, ready to be dumped on a micro SD card. Launch the following
|
||||
command as root:
|
||||
|
||||
dd if=output/images/sdcard.img of=/dev/<your-sd-device>
|
||||
|
||||
*** WARNING! This will destroy all the card content. Use with care! ***
|
||||
|
||||
|
||||
Boot the QMTECH Zynq board
|
||||
==========================
|
||||
|
||||
To boot your newly created system:
|
||||
- put a mini USB cable into the J4 Debug USB Port and connect using a
|
||||
terminal emulator at 115200 bps, 8n1,
|
||||
- put the prepared micro SD card in the J2 micro SD card slot,
|
||||
- plug the 5V power supply on the JP4 barrel jack.
|
||||
|
||||
Enjoy!
|
||||
|
||||
|
||||
[1]. QMTECH:
|
||||
http://www.chinaqmtech.com/
|
||||
|
||||
[2]. QMTECH Zynq XC7Z010 Starter Kit Product Page:
|
||||
http://www.chinaqmtech.com/xilinx_zynq_soc
|
||||
|
||||
[3]. QMTECH Zynq XC7Z010 Starter Kit Hardware User Manual:
|
||||
http://www.chinaqmtech.com/filedownload/32552
|
||||
|
||||
[4]. QMTECH Github:
|
||||
https://github.com/ChinaQMTECH/ZYNQ_STARTER_KIT
|
||||
@ -1,33 +0,0 @@
|
||||
BR2_arm=y
|
||||
BR2_cortex_a9=y
|
||||
BR2_ARM_ENABLE_NEON=y
|
||||
BR2_ARM_ENABLE_VFP=y
|
||||
BR2_GLOBAL_PATCH_DIR="board/qmtech/zynq/patches"
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_19=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="ttyPS0"
|
||||
BR2_ROOTFS_POST_BUILD_SCRIPT="board/zynq/post-build.sh"
|
||||
BR2_ROOTFS_POST_IMAGE_SCRIPT="board/zynq/post-image.sh"
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xilinx-v2019.2.01)/linux-xilinx-v2019.2.01.tar.gz"
|
||||
BR2_LINUX_KERNEL_DEFCONFIG="xilinx_zynq"
|
||||
BR2_LINUX_KERNEL_UIMAGE=y
|
||||
BR2_LINUX_KERNEL_UIMAGE_LOADADDR="0x8000"
|
||||
BR2_LINUX_KERNEL_DTS_SUPPORT=y
|
||||
BR2_LINUX_KERNEL_INTREE_DTS_NAME="zynq-qmtech"
|
||||
BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
|
||||
BR2_TARGET_ROOTFS_EXT2=y
|
||||
BR2_TARGET_ROOTFS_EXT2_4=y
|
||||
BR2_TARGET_UBOOT=y
|
||||
BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
|
||||
BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
|
||||
BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,jolivain,u-boot-xlnx,xilinx-v2019.2.qmtech.1)/uboot-xilinx-v2019.2.qmtech.1.tar.gz"
|
||||
BR2_TARGET_UBOOT_BOARD_DEFCONFIG="zynq_qmtech"
|
||||
BR2_TARGET_UBOOT_NEEDS_DTC=y
|
||||
BR2_TARGET_UBOOT_NEEDS_OPENSSL=y
|
||||
BR2_TARGET_UBOOT_FORMAT_IMG=y
|
||||
BR2_TARGET_UBOOT_SPL=y
|
||||
BR2_TARGET_UBOOT_SPL_NAME="spl/boot.bin"
|
||||
BR2_PACKAGE_HOST_DOSFSTOOLS=y
|
||||
BR2_PACKAGE_HOST_GENIMAGE=y
|
||||
BR2_PACKAGE_HOST_MTOOLS=y
|
||||
Loading…
Reference in New Issue
Block a user