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configs/zynqmp: bump to xilinx-v2023.1

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This patch bumps the zynqmp defconfigs to xilinx-v2023.1 which includes
the following updates:

- Linux v6.1.5
- U-Boot v2023.01
- ATF v2.8 (including mainline buildroot patches)
- PMUFW xilinx_v2023.1
- Updated pm_cfg_obj.c from Vitis v2023.1
- Removed kria u-boot patch which is included with xilinx-v2023.1

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
This commit is contained in:
Neal Frager 2023-08-02 06:55:46 +01:00 committed by Thomas Petazzoni
parent 8aa64eecb0
commit 78039eb59a
10 changed files with 39 additions and 209 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.checkpackageignore
View File

@ -101,7 +101,6 @@ board/udoo/common/post-build.sh Shellcheck
board/udoo/mx6qdl/patches/linux/0000-udoo-disable-usbh1.patch Upstream
board/versal/post-build.sh Shellcheck
board/versal/post-image.sh Shellcheck TrailingSpace
board/zynqmp/kria/patches/uboot/v1-0001-makefile-add-multi_dtb_fit-dep.patch ApplyOrder Upstream
boot/afboot-stm32/0003-Makefile-disable-stack-protector.patch Upstream
boot/at91bootstrap/0001-eabi-fix.patch Upstream
boot/at91bootstrap/0002-gcc-4.6.x-ldscript-fix.patch Upstream

69
board/zynqmp/kria/kv260/pm_cfg_obj.c
View File

@ -30,6 +30,9 @@
#define SUSPEND_TIMEOUT 0xFFFFFFFFU
#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001
#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100
#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200
@ -51,7 +54,7 @@ __root const u32 XPm_ConfigObject[] =
/* HEADER */
2, /* Number of remaining words in the header */
8, /* Number of sections included in config object */
1U, /* Type of config object as base */
PM_CONFIG_OBJECT_TYPE_BASE, /* Type of config object as base */
/**********************************************************************/
/* MASTER SECTION */
PM_CONFIG_MASTER_SECTION_ID, /* Master SectionID */
@ -81,7 +84,7 @@ __root const u32 XPm_ConfigObject[] =
PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */
49, /* Number of slaves */
34, /* Number of slaves */
NODE_OCM_BANK_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
@ -131,10 +134,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_USB_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_TTC_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -151,54 +150,22 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_SATA,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_ETH_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_ETH_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_ETH_2,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_ETH_3,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_UART_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_UART_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_SPI_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_SPI_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_I2C_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_I2C_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_SD_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_SD_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -215,10 +182,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_NAND,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_QSPI,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -227,14 +190,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_CAN_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_CAN_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_EXTERN,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -259,22 +214,10 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_PCIE,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_PCAP,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_RTC,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_VCU,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_PL,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -545,8 +488,6 @@ __root const u32 XPm_ConfigObject[] =
/**********************************************************************/
/* GPO SECTION */
PM_CONFIG_GPO_SECTION_ID, /* GPO Section ID */
PM_CONFIG_GPO1_BIT_2_MASK |
PM_CONFIG_GPO1_MIO_PIN_34_MAP |
PM_CONFIG_GPO1_MIO_PIN_35_MAP |
0, /* State of GPO pins */
};

32
board/zynqmp/kria/patches/uboot/v1-0001-makefile-add-multi_dtb_fit-dep.patch
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@ -1,32 +0,0 @@
From 8b181bf582c17cf709a62cf499f9709c94f49d33 Mon Sep 17 00:00:00 2001
From: Neal Frager <neal.frager@amd.com>
Date: Wed, 21 Dec 2022 07:51:42 +0000
Subject: [PATCH v1 1/1] makefile: add multi_dtb_fit dep
With certain gcc compilers, the u-boot.itb is built immediately after dtb
generation. If CONFIG_MULTI_DTB_FIT is used, it is possible that the
fit-dtb.blob is not finished in time.
This patch adds a necessary dependency to guarantee that the fit-dtb.blob
is built before attempting to build the u-boot.itb.
Signed-off-by: Neal Frager <neal.frager@amd.com>
---
Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/Makefile b/Makefile
index b96e2ffa15..682a5d94fd 100644
--- a/Makefile
+++ b/Makefile
@@ -1425,6 +1425,7 @@ MKIMAGEFLAGS_u-boot.itb += -B 0x8
ifdef U_BOOT_ITS
u-boot.itb: u-boot-nodtb.bin \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX),dts/dt.dtb) \
+ $(if $(CONFIG_MULTI_DTB_FIT),$(FINAL_DTB_CONTAINER)) \
$(U_BOOT_ITS) FORCE
$(call if_changed,mkfitimage)
$(BOARD_SIZE_CHECK)
--
2.17.1

2
board/zynqmp/patches/arm-trusted-firmware/0001-feat-build-add-support-for-new-binutils-versions.patch
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@ -1 +1 @@
../../../../boot/arm-trusted-firmware/v2.6/0001-feat-build-add-support-for-new-binutils-versions.patch
../../../../boot/arm-trusted-firmware/v2.8/0001-feat-build-add-support-for-new-binutils-versions.patch

1
board/zynqmp/patches/arm-trusted-firmware/0002-build-tools-avoid-unnecessary-link.patch Symbolic link
View File

@ -0,0 +1 @@
../../../../boot/arm-trusted-firmware/v2.8/0002-build-tools-avoid-unnecessary-link.patch

51
board/zynqmp/zcu102/pm_cfg_obj.c
View File

@ -30,6 +30,9 @@
#define SUSPEND_TIMEOUT 0xFFFFFFFFU
#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001
#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100
#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200
@ -51,7 +54,7 @@ __root const u32 XPm_ConfigObject[] =
/* HEADER */
2, /* Number of remaining words in the header */
8, /* Number of sections included in config object */
1U, /* Type of config object as base */
PM_CONFIG_OBJECT_TYPE_BASE, /* Type of config object as base */
/**********************************************************************/
/* MASTER SECTION */
PM_CONFIG_MASTER_SECTION_ID, /* Master SectionID */
@ -81,7 +84,7 @@ __root const u32 XPm_ConfigObject[] =
PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */
49, /* Number of slaves */
38, /* Number of slaves */
NODE_OCM_BANK_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
@ -131,10 +134,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_USB_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_TTC_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -155,18 +154,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_ETH_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_ETH_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_ETH_2,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_ETH_3,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -179,14 +166,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_SPI_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_SPI_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_I2C_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -195,10 +174,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_SD_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_SD_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -215,10 +190,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_NAND,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_QSPI,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -227,10 +198,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_CAN_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_CAN_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -263,18 +230,10 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_PCAP,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_RTC,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_VCU,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_PL,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */

51
board/zynqmp/zcu106/pm_cfg_obj.c
View File

@ -30,6 +30,9 @@
#define SUSPEND_TIMEOUT 0xFFFFFFFFU
#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001
#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100
#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200
@ -51,7 +54,7 @@ __root const u32 XPm_ConfigObject[] =
/* HEADER */
2, /* Number of remaining words in the header */
8, /* Number of sections included in config object */
1U, /* Type of config object as base */
PM_CONFIG_OBJECT_TYPE_BASE, /* Type of config object as base */
/**********************************************************************/
/* MASTER SECTION */
PM_CONFIG_MASTER_SECTION_ID, /* Master SectionID */
@ -81,7 +84,7 @@ __root const u32 XPm_ConfigObject[] =
PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */
49, /* Number of slaves */
38, /* Number of slaves */
NODE_OCM_BANK_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
@ -131,10 +134,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_USB_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_TTC_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -155,18 +154,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_ETH_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_ETH_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_ETH_2,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_ETH_3,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -179,14 +166,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_SPI_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_SPI_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_I2C_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -195,10 +174,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_SD_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_SD_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -215,10 +190,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_NAND,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_QSPI,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -227,10 +198,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_CAN_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_CAN_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@ -259,14 +226,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
NODE_PCIE,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_PCAP,
PM_SLAVE_FLAG_IS_SHAREABLE,
0U, /* IPI Mask */
NODE_RTC,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */

15
configs/zynqmp_kria_kv260_defconfig
View File

@ -1,12 +1,12 @@
BR2_aarch64=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_15=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_1=y
BR2_ROOTFS_POST_BUILD_SCRIPT="board/zynqmp/post-build.sh board/zynqmp/kria/kv260/kv260.sh"
BR2_ROOTFS_POST_IMAGE_SCRIPT="board/zynqmp/post-image.sh"
BR2_ROOTFS_POST_SCRIPT_ARGS="ttyPS1,115200 mmcblk1p2 ${UBOOT_DIR}"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xlnx_rebase_v5.15_LTS_2022.2)/xlnx_rebase_v5.15_LTS_2022.2.tar.gz"
BR2_LINUX_KERNEL_DEFCONFIG="xilinx_zynqmp"
BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xlnx_rebase_v6.1_LTS_2023.1)/xlnx_rebase_v6.1_LTS_2023.1.tar.gz"
BR2_LINUX_KERNEL_DEFCONFIG="xilinx"
BR2_LINUX_KERNEL_DTS_SUPPORT=y
BR2_LINUX_KERNEL_INTREE_DTS_NAME="xilinx/zynqmp-smk-k26-revA-sck-kv-g-revB"
BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
@ -15,27 +15,28 @@ BR2_TARGET_ROOTFS_EXT2_4=y
# BR2_TARGET_ROOTFS_TAR is not set
BR2_TARGET_ARM_TRUSTED_FIRMWARE=y
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL=y
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,arm-trusted-firmware,xlnx_rebase_v2.6_2022.2)/xlnx_rebase_v2.6_2022.2.tar.gz"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,arm-trusted-firmware,xlnx_rebase_v2.8_2023.1)/xlnx_rebase_v2.8_2023.1.tar.gz"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="zynqmp"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_ADDITIONAL_VARIABLES="ZYNQMP_CONSOLE=cadence1"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_BL31_UBOOT=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,u-boot-xlnx,xlnx_rebase_v2022.01_2022.2)/xlnx_rebase_v2022.01_2022.2.tar.gz"
BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,u-boot-xlnx,xlnx_rebase_v2023.01_2023.1)/xlnx_rebase_v2023.01_2023.1.tar.gz"
BR2_TARGET_UBOOT_BOARD_DEFCONFIG="xilinx_zynqmp_virt"
BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES="board/zynqmp/kria/uboot.fragment"
BR2_TARGET_UBOOT_CUSTOM_MAKEOPTS="DEVICE_TREE=zynqmp-smk-k26-revA"
BR2_TARGET_UBOOT_NEEDS_DTC=y
BR2_TARGET_UBOOT_NEEDS_OPENSSL=y
BR2_TARGET_UBOOT_NEEDS_GNUTLS=y
BR2_TARGET_UBOOT_SPL=y
BR2_TARGET_UBOOT_SPL_NAME="spl/boot.bin"
BR2_TARGET_UBOOT_ZYNQMP=y
BR2_TARGET_UBOOT_ZYNQMP_PMUFW="https://github.com/Xilinx/ubuntu-firmware/raw/2022.2_br_1/kv260/kv260_pmufw.elf"
BR2_TARGET_UBOOT_ZYNQMP_PMUFW="https://github.com/Xilinx/soc-prebuilt-firmware/raw/xilinx_v2023.1/kv260-kria/pmufw.elf"
BR2_TARGET_UBOOT_ZYNQMP_PM_CFG="board/zynqmp/kria/kv260/pm_cfg_obj.c"
BR2_TARGET_UBOOT_FORMAT_ITB=y
BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y
BR2_PACKAGE_HOST_DOSFSTOOLS=y
BR2_PACKAGE_HOST_GENIMAGE=y
BR2_PACKAGE_HOST_MTOOLS=y
BR2_GLOBAL_PATCH_DIR="board/zynqmp/kria/patches board/zynqmp/patches"
BR2_GLOBAL_PATCH_DIR="board/zynqmp/patches"

13
configs/zynqmp_zcu102_defconfig
View File

@ -1,12 +1,12 @@
BR2_aarch64=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_15=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_1=y
BR2_ROOTFS_POST_BUILD_SCRIPT="board/zynqmp/post-build.sh"
BR2_ROOTFS_POST_IMAGE_SCRIPT="board/zynqmp/post-image.sh"
BR2_ROOTFS_POST_SCRIPT_ARGS="ttyPS0,115200 mmcblk0p2"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xlnx_rebase_v5.15_LTS_2022.2)/xlnx_rebase_v5.15_LTS_2022.2.tar.gz"
BR2_LINUX_KERNEL_DEFCONFIG="xilinx_zynqmp"
BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xlnx_rebase_v6.1_LTS_2023.1)/xlnx_rebase_v6.1_LTS_2023.1.tar.gz"
BR2_LINUX_KERNEL_DEFCONFIG="xilinx"
BR2_LINUX_KERNEL_DTS_SUPPORT=y
BR2_LINUX_KERNEL_INTREE_DTS_NAME="xilinx/zynqmp-zcu102-rev1.0"
BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
@ -15,21 +15,22 @@ BR2_TARGET_ROOTFS_EXT2_4=y
# BR2_TARGET_ROOTFS_TAR is not set
BR2_TARGET_ARM_TRUSTED_FIRMWARE=y
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL=y
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,arm-trusted-firmware,xlnx_rebase_v2.6_2022.2)/xlnx_rebase_v2.6_2022.2.tar.gz"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,arm-trusted-firmware,xlnx_rebase_v2.8_2023.1)/xlnx_rebase_v2.8_2023.1.tar.gz"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="zynqmp"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_BL31_UBOOT=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,u-boot-xlnx,xlnx_rebase_v2022.01_2022.2)/xlnx_rebase_v2022.01_2022.2.tar.gz"
BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,u-boot-xlnx,xlnx_rebase_v2023.01_2023.1)/xlnx_rebase_v2023.01_2023.1.tar.gz"
BR2_TARGET_UBOOT_BOARD_DEFCONFIG="xilinx_zynqmp_virt"
BR2_TARGET_UBOOT_CUSTOM_MAKEOPTS="DEVICE_TREE=zynqmp-zcu102-rev1.0"
BR2_TARGET_UBOOT_NEEDS_DTC=y
BR2_TARGET_UBOOT_NEEDS_OPENSSL=y
BR2_TARGET_UBOOT_NEEDS_GNUTLS=y
BR2_TARGET_UBOOT_SPL=y
BR2_TARGET_UBOOT_SPL_NAME="spl/boot.bin"
BR2_TARGET_UBOOT_ZYNQMP=y
BR2_TARGET_UBOOT_ZYNQMP_PMUFW="https://github.com/Xilinx/ubuntu-firmware/raw/2022.2_br_1/zcu102/zcu102_pmufw.elf"
BR2_TARGET_UBOOT_ZYNQMP_PMUFW="https://github.com/Xilinx/soc-prebuilt-firmware/raw/xilinx_v2023.1/zcu102-zynqmp/pmufw.elf"
BR2_TARGET_UBOOT_ZYNQMP_PM_CFG="board/zynqmp/zcu102/pm_cfg_obj.c"
BR2_TARGET_UBOOT_FORMAT_ITB=y
BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y

13
configs/zynqmp_zcu106_defconfig
View File

@ -1,12 +1,12 @@
BR2_aarch64=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_15=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_1=y
BR2_ROOTFS_POST_BUILD_SCRIPT="board/zynqmp/post-build.sh"
BR2_ROOTFS_POST_IMAGE_SCRIPT="board/zynqmp/post-image.sh"
BR2_ROOTFS_POST_SCRIPT_ARGS="ttyPS0,115200 mmcblk0p2"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xlnx_rebase_v5.15_LTS_2022.2)/xlnx_rebase_v5.15_LTS_2022.2.tar.gz"
BR2_LINUX_KERNEL_DEFCONFIG="xilinx_zynqmp"
BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xlnx_rebase_v6.1_LTS_2023.1)/xlnx_rebase_v6.1_LTS_2023.1.tar.gz"
BR2_LINUX_KERNEL_DEFCONFIG="xilinx"
BR2_LINUX_KERNEL_DTS_SUPPORT=y
BR2_LINUX_KERNEL_INTREE_DTS_NAME="xilinx/zynqmp-zcu106-revA"
BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
@ -15,21 +15,22 @@ BR2_TARGET_ROOTFS_EXT2_4=y
# BR2_TARGET_ROOTFS_TAR is not set
BR2_TARGET_ARM_TRUSTED_FIRMWARE=y
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL=y
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,arm-trusted-firmware,xlnx_rebase_v2.6_2022.2)/xlnx_rebase_v2.6_2022.2.tar.gz"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,arm-trusted-firmware,xlnx_rebase_v2.8_2023.1)/xlnx_rebase_v2.8_2023.1.tar.gz"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="zynqmp"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_BL31_UBOOT=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,u-boot-xlnx,xlnx_rebase_v2022.01_2022.2)/xlnx_rebase_v2022.01_2022.2.tar.gz"
BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,u-boot-xlnx,xlnx_rebase_v2023.01_2023.1)/xlnx_rebase_v2023.01_2023.1.tar.gz"
BR2_TARGET_UBOOT_BOARD_DEFCONFIG="xilinx_zynqmp_virt"
BR2_TARGET_UBOOT_CUSTOM_MAKEOPTS="DEVICE_TREE=zynqmp-zcu106-revA"
BR2_TARGET_UBOOT_NEEDS_DTC=y
BR2_TARGET_UBOOT_NEEDS_OPENSSL=y
BR2_TARGET_UBOOT_NEEDS_GNUTLS=y
BR2_TARGET_UBOOT_SPL=y
BR2_TARGET_UBOOT_SPL_NAME="spl/boot.bin"
BR2_TARGET_UBOOT_ZYNQMP=y
BR2_TARGET_UBOOT_ZYNQMP_PMUFW="https://github.com/Xilinx/ubuntu-firmware/raw/2022.2_br_1/zcu106/zcu106_pmufw.elf"
BR2_TARGET_UBOOT_ZYNQMP_PMUFW="https://github.com/Xilinx/soc-prebuilt-firmware/raw/xilinx_v2023.1/zcu106-zynqmp/pmufw.elf"
BR2_TARGET_UBOOT_ZYNQMP_PM_CFG="board/zynqmp/zcu106/pm_cfg_obj.c"
BR2_TARGET_UBOOT_FORMAT_ITB=y
BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y