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configs/octavo_osd32mp1_red: new defconfig

Browse Source 
This patch adds support for the Octavo Systems RED board. We use the
TF-A, U-Boot and Linux versions from ST, Device Trees from Octavo, as
well as a U-Boot patch from Octavo.

Reference:

  https://octavosystems.com/octavo_products/osd32mp1-red/

The device tree blobs come from Octavo System:

  https://github.com/octavosystems/OSD32MP1-RED-Device-tree.git

The uboot patches come from Octavo System:

  395ebd1f48/patches/u-boot-2018.11

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
This commit is contained in:
Kory Maincent 2021-11-30 11:39:19 +01:00 committed by Thomas Petazzoni
parent 0380696669
commit 672807b815
11 changed files with 6168 additions and 0 deletions
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2
DEVELOPERS
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@ -1656,7 +1656,9 @@ F: package/linuxconsoletools/
N: Kory Maincent <kory.maincent@bootlin.com>
F: board/octavo/osd32mp1-brk/
F: board/octavo/osd32mp1-red/
F: configs/octavo_osd32mp1_brk_defconfig
F: configs/octavo_osd32mp1_red_defconfig
N: Kurt Van Dijck <dev.kurt@vandijck-laurijssen.be>
F: package/bcusdk/

23
board/octavo/osd32mp1-red/genimage.cfg Normal file
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image sdcard.img {
hdimage {
gpt = "true"
}
partition fsbl1 {
image = "tf-a-osd32mp1-red.stm32"
}
partition fsbl2 {
image = "tf-a-osd32mp1-red.stm32"
}
partition ssbl {
image = "u-boot.stm32"
size = 2M
}
partition rootfs {
image = "rootfs.ext4"
bootable = "yes"
}
}

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board/octavo/osd32mp1-red/linux-dts/osd32mp1-red.dts Normal file
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board/octavo/osd32mp1-red/linux-dts/stm32mp157c-osd32mp1-red.dtsi Normal file
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board/octavo/osd32mp1-red/overlay/boot/extlinux/extlinux.conf Normal file
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label osd32mp1-red-buildroot
kernel /boot/zImage
devicetree /boot/osd32mp1-red.dtb
append root=/dev/mmcblk1p4 rootwait

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board/octavo/osd32mp1-red/patches/uboot/0001-Add-OSD32MP1-RED-Device-Tree-support.patch Normal file
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32
board/octavo/osd32mp1-red/patches/uboot/0002-configs-stm32mp15_trusted_defconfig-disable-environm.patch Normal file
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From 3feee3e00dcb9467b5345671300e7c73f3e05f93 Mon Sep 17 00:00:00 2001
From: Kory Maincent <kory.maincent@bootlin.com>
Date: Tue, 5 Oct 2021 14:31:28 +0200
Subject: [PATCH 2/2] configs/stm32mp15_trusted_defconfig: disable environment
select only ENV_IS_NOWHERE
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
---
configs/stm32mp15_trusted_defconfig | 6 ------
1 file changed, 6 deletions(-)
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 7635d7f6c7..6ec4bcd080 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -38,12 +38,6 @@ CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_ENV_IS_NOWHERE=y
-CONFIG_ENV_IS_IN_EXT4=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_IS_IN_UBI=y
-CONFIG_ENV_EXT4_INTERFACE="mmc"
-CONFIG_ENV_EXT4_DEVICE_AND_PART="0:auto"
-CONFIG_ENV_EXT4_FILE="/uboot.env"
CONFIG_STM32_ADC=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
--
2.25.1

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board/octavo/osd32mp1-red/readme.txt Normal file
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OSD32MP1-RED
Intro
=====
This configuration supports the OSD32MP1-RED platform:
https://octavosystems.com/octavo_products/osd32mp1-red/
How to build
============
$ make octavo_osd32mp1_red_defconfig
$ make
How to write the microSD card
=============================
Once the build process is finished you will have an image called
"sdcard.img" in the output/images/ directory.
Copy the bootable "sdcard.img" onto an microSD card with "dd":
$ sudo dd if=output/images/sdcard.img of=/dev/sdX
Boot the board
==============
(1) Insert the microSD card in connector X5.
(2) Plug an USB-SERIAL cable in the JP4 pin connector and run your serial
communication program on /dev/ttySTM0.
(3) Plug an USB-C cable in the J2 connector or use barrel power supply to
power-up the board.
(4) The system will start, with the console on UART.

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board/octavo/osd32mp1-red/tfa-dts/osd32mp1-red.dts Normal file
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (C) STMicroelectronics 2020 - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics.
*/
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
/dts-v1/;
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-osd32mp1-ddr3-1x4Gb-1066-binG.dtsi"
#include "stm32mp157c.dtsi"
#include "stm32mp157cac-pinctrl.dtsi"
#include "stm32mp15-ddr.dtsi"
#include "stm32mp157c-security.dtsi"
#include <dt-bindings/power/stm32mp1-power.h>
/ {
model = "Octavo OSD32MP1-RED board";
compatible = "octavo,osd32mp1-red", "st,stm32mp157";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio25 = &gpioz;
i2c3 = &i2c4;
};
clocks {
clk_lse: clk-lse {
st,drive = < LSEDRV_MEDIUM_HIGH >;
};
clk_hse: clk-hse {
st,digbypass;
};
};
}; /*root*/
&pinctrl {
sdmmc1_pins_mx: sdmmc1_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
};
sdmmc2_pins_mx: sdmmc2_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
<STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
<STM32_PINMUX('C', 7, AF10)>, /* SDMMC2_D7 */
<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
bias-pull-up;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
bias-pull-up;
drive-push-pull;
slew-rate = <2>;
};
};
sdmmc3_pins_mx: sdmmc3_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
<STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
<STM32_PINMUX('F', 1, AF9)>, /* SDMMC3_CMD */
<STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
<STM32_PINMUX('F', 5, AF9)>; /* SDMMC3_D2 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
uart4_pins_mx: uart4_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
};
};
&pinctrl_z {
i2c4_pins_z_mx: i2c4_mx-0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
};
&rcc {
st,csi-cal;
st,hsi-cal;
st,cal-sec = <60>;
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
0 /*MCU*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;
st,pkcs = <
CLK_CKPER_HSE
CLK_ETH_PLL3Q
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_DISABLED
CLK_SPI2S23_PLL3Q
CLK_SPI45_PCLK2
CLK_SPI6_DISABLED
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_DISABLED
CLK_I2C12_HSI
CLK_I2C35_PCLK1
CLK_UART1_DISABLED
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_DISABLED
CLK_UART78_DISABLED
CLK_SPDIF_DISABLED
CLK_SAI1_DISABLED
CLK_SAI2_CKPER
CLK_SAI3_DISABLED
CLK_SAI4_DISABLED
CLK_RNG1_LSI
CLK_LPTIM1_DISABLED
CLK_LPTIM23_DISABLED
CLK_LPTIM45_DISABLED
>;
pll1:st,pll@0 {
cfg = < 2 80 0 1 1 PQR(1,0,0) >;
frac = < 0x800>;
};
pll2:st,pll@1 {
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400>;
};
pll3:st,pll@2 {
cfg = < 1 61 3 5 36 PQR(1,1,0) >;
frac = < 0x1000 >;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
};
};
&bsec{
status = "okay";
secure-status = "okay";
board_id: board_id@ec {
reg = <0xec 0x4>;
status = "okay";
secure-status = "okay";
};
};
&etzpc{
st,decprot = <
/*"Non Secured" peripherals*/
DECPROT(STM32MP1_ETZPC_DCMI_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SPI2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SAI2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SDMMC3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_DLYBSD3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SPI5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_TIM5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_UART4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_USART2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
/*Restriction: following IDs are not managed - please to use User-Section if needed:
STM32MP1_ETZPC_DMA1_ID, STM32MP1_ETZPC_DMA2_ID, STM32MP1_ETZPC_DMAMUX_ID,
STM32MP1_ETZPC_SRAMx_ID, STM32MP1_ETZPC_RETRAM_ID, STM32MP1_ETZPC_BKPSRAM_ID*/
/*STM32CubeMX generates a basic and standard configuration for ETZPC.
Additional device configurations can be added here if needed.
"etzpc" node could be also overloaded in "addons" User-Section.*/
>;
secure-status = "okay";
};
&i2c4{
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_z_mx>;
status = "okay";
secure-status = "okay";
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
st,main-control-register = <0x04>;
st,vin-control-register = <0xc0>;
st,usb-control-register = <0x20>;
regulators {
compatible = "st,stpmic1-regulators";
ldo1-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
ldo6-supply = <&v3v3>;
vddcore: buck1 {
regulator-name = "vddcore";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
lp-stop {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1200000>;
};
standby-ddr-sr {
regulator-off-in-suspend;
};
standby-ddr-off {
regulator-off-in-suspend;
};
};
vdd_ddr: buck2 {
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
lp-stop {
regulator-suspend-microvolt = <1350000>;
regulator-on-in-suspend;
};
standby-ddr-sr {
regulator-suspend-microvolt = <1350000>;
regulator-on-in-suspend;
};
standby-ddr-off {
regulator-off-in-suspend;
};
};
vdd: buck3 {
regulator-name = "vdd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
st,mask-reset;
regulator-initial-mode = <0>;
regulator-over-current-protection;
lp-stop {
regulator-suspend-microvolt = <3300000>;
regulator-on-in-suspend;
};
standby-ddr-sr {
regulator-suspend-microvolt = <3300000>;
regulator-on-in-suspend;
};
standby-ddr-off {
regulator-suspend-microvolt = <3300000>;
regulator-on-in-suspend;
};
};
v3v3: buck4 {
regulator-name = "v3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-over-current-protection;
regulator-initial-mode = <0>;
lp-stop {
regulator-suspend-microvolt = <3300000>;
regulator-on-in-suspend;
};
standby-ddr-sr {
regulator-off-in-suspend;
};
standby-ddr-off {
regulator-off-in-suspend;
};
};
v1v8_audio: ldo1 {
regulator-name = "v1v8_audio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
standby-ddr-sr {
regulator-off-in-suspend;
};
standby-ddr-off {
regulator-off-in-suspend;
};
};
v3v3_hdmi: ldo2 {
regulator-name = "v3v3_hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
standby-ddr-sr {
regulator-off-in-suspend;
};
standby-ddr-off {
regulator-off-in-suspend;
};
};
vtt_ddr: ldo3 {
regulator-name = "vtt_ddr";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <750000>;
regulator-always-on;
regulator-over-current-protection;
lp-stop {
regulator-off-in-suspend;
};
standby-ddr-sr {
regulator-off-in-suspend;
};
standby-ddr-off {
regulator-off-in-suspend;
};
};
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
standby-ddr-sr {
regulator-off-in-suspend;
};
standby-ddr-off {
regulator-off-in-suspend;
};
};
vdda: ldo5 {
regulator-name = "vdda";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
regulator-boot-on;
standby-ddr-sr {
regulator-off-in-suspend;
};
standby-ddr-off {
regulator-off-in-suspend;
};
};
v1v2_hdmi: ldo6 {
regulator-name = "v1v2_hdmi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
standby-ddr-sr {
regulator-off-in-suspend;
};
standby-ddr-off {
regulator-off-in-suspend;
};
};
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
regulator-over-current-protection;
lp-stop {
regulator-on-in-suspend;
};
standby-ddr-sr {
regulator-on-in-suspend;
};
standby-ddr-off {
regulator-off-in-suspend;
};
};
};
};
};
&iwdg2{
status = "okay";
secure-status = "okay";
timeout-sec = <32>;
};
&pwr{
status = "okay";
secure-status = "okay";
system_suspend_supported_soc_modes = <
STM32_PM_CSLEEP_RUN
STM32_PM_CSTOP_ALLOW_LP_STOP
STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR
>;
system_off_soc_mode = <STM32_PM_CSTOP_ALLOW_STANDBY_DDR_OFF>;
pwr-regulators {
vdd-supply = <&vdd>;
};
};
&rcc{
status = "okay";
secure-status = "okay";
};
&rng1{
status = "okay";
secure-status = "okay";
};
&rtc{
status = "okay";
secure-status = "okay";
};
&sdmmc1{
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_pins_mx>;
status = "okay";
broken-cd;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
};
&sdmmc2{
pinctrl-names = "default";
pinctrl-0 = <&sdmmc2_pins_mx>;
status = "okay";
};
&sdmmc3{
pinctrl-names = "default";
pinctrl-0 = <&sdmmc3_pins_mx>;
status = "okay";
};
&tamp{
status = "okay";
secure-status = "okay";
};
&uart4{
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_mx>;
status = "okay";
};
/delete-node/ &qspi_bk1_pins_a;
/delete-node/ &qspi_bk2_pins_a;
/delete-node/ &qspi_clk_pins_a;
/delete-node/ &sdmmc1_b4_pins_a;
/delete-node/ &sdmmc1_dir_pins_a;
/delete-node/ &sdmmc1_dir_pins_b;
/delete-node/ &sdmmc2_b4_pins_a;
/delete-node/ &sdmmc2_d47_pins_a;
/delete-node/ &uart4_pins_a;
/delete-node/ &uart7_pins_a;
/delete-node/ &usart3_pins_a;
/delete-node/ &usart3_pins_b;
/delete-node/ &i2c4_pins_a;

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board/octavo/osd32mp1-red/tfa-dts/stm32mp15-osd32mp1-ddr3-1x4Gb-1066-binG.dtsi Normal file
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/*
* Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
*
*/
/*
* File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
* DDR type: DDR3 / DDR3L
* DDR width: 16bits
* DDR density: 4Gb
* System frequency: 533000Khz
* Relaxed Timing Mode: false
* Address mapping type: RBC
*
* Save Date: 2020.02.08, save Time: 23:22:33
*/
#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000
#define DDR_MSTR 0x00041401
#define DDR_MRCTRL0 0x00000010
#define DDR_MRCTRL1 0x00000000
#define DDR_DERATEEN 0x00000000
#define DDR_DERATEINT 0x00800000
#define DDR_PWRCTL 0x00000000
#define DDR_PWRTMG 0x00400010
#define DDR_HWLPCTL 0x00000000
#define DDR_RFSHCTL0 0x00210000
#define DDR_RFSHCTL3 0x00000000
#define DDR_RFSHTMG 0x0081008B
#define DDR_CRCPARCTL0 0x00000000
#define DDR_DRAMTMG0 0x121B2414
#define DDR_DRAMTMG1 0x000A041C
#define DDR_DRAMTMG2 0x0608090F
#define DDR_DRAMTMG3 0x0050400C
#define DDR_DRAMTMG4 0x08040608
#define DDR_DRAMTMG5 0x06060403
#define DDR_DRAMTMG6 0x02020002
#define DDR_DRAMTMG7 0x00000202
#define DDR_DRAMTMG8 0x00001005
#define DDR_DRAMTMG14 0x000000A0
#define DDR_ZQCTL0 0xC2000040
#define DDR_DFITMG0 0x02060105
#define DDR_DFITMG1 0x00000202
#define DDR_DFILPCFG0 0x07000000
#define DDR_DFIUPD0 0xC0400003
#define DDR_DFIUPD1 0x00000000
#define DDR_DFIUPD2 0x00000000
#define DDR_DFIPHYMSTR 0x00000000
#define DDR_ODTCFG 0x06000600
#define DDR_ODTMAP 0x00000001
#define DDR_SCHED 0x00000C01
#define DDR_SCHED1 0x00000000
#define DDR_PERFHPR1 0x01000001
#define DDR_PERFLPR1 0x08000200
#define DDR_PERFWR1 0x08000400
#define DDR_DBG0 0x00000000
#define DDR_DBG1 0x00000000
#define DDR_DBGCMD 0x00000000
#define DDR_POISONCFG 0x00000000
#define DDR_PCCFG 0x00000010
#define DDR_PCFGR_0 0x00010000
#define DDR_PCFGW_0 0x00000000
#define DDR_PCFGQOS0_0 0x02100C03
#define DDR_PCFGQOS1_0 0x00800100
#define DDR_PCFGWQOS0_0 0x01100C03
#define DDR_PCFGWQOS1_0 0x01000200
#define DDR_PCFGR_1 0x00010000
#define DDR_PCFGW_1 0x00000000
#define DDR_PCFGQOS0_1 0x02100C03
#define DDR_PCFGQOS1_1 0x00800040
#define DDR_PCFGWQOS0_1 0x01100C03
#define DDR_PCFGWQOS1_1 0x01000200
#define DDR_ADDRMAP1 0x00070707
#define DDR_ADDRMAP2 0x00000000
#define DDR_ADDRMAP3 0x1F000000
#define DDR_ADDRMAP4 0x00001F1F
#define DDR_ADDRMAP5 0x06060606
#define DDR_ADDRMAP6 0x0F060606
#define DDR_ADDRMAP9 0x00000000
#define DDR_ADDRMAP10 0x00000000
#define DDR_ADDRMAP11 0x00000000
#define DDR_PGCR 0x01442E02
#define DDR_PTR0 0x0022AA5B
#define DDR_PTR1 0x04841104
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
#define DDR_DSGCR 0xF200011F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x38D488D0
#define DDR_DTPR1 0x098B00D8
#define DDR_DTPR2 0x10023600
#define DDR_MR0 0x00000840
#define DDR_MR1 0x00000000
#define DDR_MR2 0x00000208
#define DDR_MR3 0x00000000
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE80
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE80
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000

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configs/octavo_osd32mp1_red_defconfig Normal file
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# architecture
BR2_arm=y
BR2_cortex_a7=y
# global patch directory
BR2_GLOBAL_PATCH_DIR="board/octavo/osd32mp1-red/patches"
# Linux headers same as kernel, a 4.19 series
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_19=y
# rootfs overlay
BR2_ROOTFS_OVERLAY="board/octavo/osd32mp1-red/overlay/"
# image generation
BR2_ROOTFS_POST_IMAGE_SCRIPT="support/scripts/genimage.sh"
BR2_ROOTFS_POST_SCRIPT_ARGS="-c board/octavo/osd32mp1-red/genimage.cfg"
# Kernel, use CUSTOM_DTS_PATH associated with INTREE_DTS_NAME to build the right
# device-tree
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_GIT=y
BR2_LINUX_KERNEL_CUSTOM_REPO_URL="https://github.com/STMicroelectronics/linux.git"
BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="v4.19-stm32mp-r3.3"
BR2_LINUX_KERNEL_DEFCONFIG="multi_v7"
BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(LINUX_DIR)/arch/arm/configs/fragment-01-multiv7_cleanup.config $(LINUX_DIR)/arch/arm/configs/fragment-02-multiv7_addons.config"
BR2_LINUX_KERNEL_DTS_SUPPORT=y
BR2_LINUX_KERNEL_INTREE_DTS_NAME="osd32mp1-red"
BR2_LINUX_KERNEL_CUSTOM_DTS_PATH="board/octavo/osd32mp1-red/linux-dts/*"
BR2_LINUX_KERNEL_INSTALL_TARGET=y
BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
# Filesystem
BR2_TARGET_ROOTFS_EXT2=y
BR2_TARGET_ROOTFS_EXT2_4=y
# BR2_TARGET_ROOTFS_TAR is not set
# TF-A
BR2_TARGET_ARM_TRUSTED_FIRMWARE=y
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_GIT=y
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_REPO_URL="https://github.com/STMicroelectronics/arm-trusted-firmware.git"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_REPO_VERSION="v2.0-stm32mp-r1.5"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="stm32mp1"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_DTS_PATH="board/octavo/osd32mp1-red/tfa-dts/*"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_ADDITIONAL_VARIABLES="STM32MP_SDMMC=1 AARCH32_SP=sp_min DTB_FILE_NAME=osd32mp1-red.dtb STM32MP_USB_PROGRAMMER=1 CFLAGS=-Wno-array-bounds"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_IMAGES="*.stm32"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_NEEDS_DTC=y
# U-Boot
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
BR2_TARGET_UBOOT_CUSTOM_GIT=y
BR2_TARGET_UBOOT_CUSTOM_REPO_URL="https://github.com/STMicroelectronics/u-boot.git"
BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="v2018.11-stm32mp-r3.2"
BR2_TARGET_UBOOT_BOARD_DEFCONFIG="stm32mp15_trusted"
# BR2_TARGET_UBOOT_FORMAT_BIN is not set
BR2_TARGET_UBOOT_FORMAT_STM32=y
BR2_TARGET_UBOOT_CUSTOM_MAKEOPTS="DEVICE_TREE=osd32mp1-red"
# Package needed to generate the image
BR2_PACKAGE_HOST_GENIMAGE=y