diff --git a/package/gcc/arc-2016.09-eng008/950-ARC-Fix-conditional-move-contstraint.patch b/package/gcc/arc-2016.09-eng008/950-ARC-Fix-conditional-move-contstraint.patch
new file mode 100644
index 0000000000..153af6d415
--- /dev/null
+++ b/package/gcc/arc-2016.09-eng008/950-ARC-Fix-conditional-move-contstraint.patch
@@ -0,0 +1,34 @@
+From e569e9c2ce2273f5175e0928efd6e45c3e71c45f Mon Sep 17 00:00:00 2001
+From: Claudiu Zissulescu <claziss@synopsys.com>
+Date: Mon, 22 Aug 2016 19:58:25 +0200
+Subject: [PATCH] [ARC] Fix conditional move contstraint
+
+Move pattern (movsi_insn) allows predicated instructions to be
+instructions which can hold all registers.  However, the conditional
+variant doesn't.  This patch fixes this problem.
+
+2016-08-22  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc.md (movsi_cond_exec): Update constraint.
+
+Signed-off-by: Claudiu Zissulescu  <claziss@synopsys.com>
+---
+ gcc/config/arc/arc.md | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
+index d87174a..607c6e6 100644
+--- a/gcc/config/arc/arc.md
++++ b/gcc/config/arc/arc.md
+@@ -3603,7 +3603,7 @@
+      (match_operator 3 "proper_comparison_operator"
+        [(match_operand 2 "cc_register" "Rcc,Rcc") (const_int 0)])
+      (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
+-	  (match_operand:SI 1 "nonmemory_operand" "Lc,?Cal")))]
++	  (match_operand:SI 1 "nonmemory_operand" "LRac,?Cal")))]
+   ""
+   "mov.%d3 %0,%S1"
+   [(set_attr "type" "cmove")
+-- 
+2.6.3
+