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configs/microchip_mpfs_icicle_defconfig: update instruction sets

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Update the instruction sets for MPFS icicle kit to mirror the
configuration update, i.e. It is now classed as a RISC-V G core with
support for C, IMAFDC.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
This commit is contained in:
Jamie Gibbons 2023-08-18 11:43:00 +01:00 committed by Yann E. MORIN
parent cbd91e89e4
commit 5e012a0704
1 changed files with 2 additions and 5 deletions
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7
configs/microchip_mpfs_icicle_defconfig
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@ -1,9 +1,6 @@
BR2_riscv=y
BR2_riscv_custom=y
BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_RVC=y
BR2_riscv_g=y
BR2_RISCV_ISA_CUSTOM_RVC=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_1=y
BR2_TARGET_GENERIC_HOSTNAME="mpfs_icicle"
BR2_ROOTFS_POST_IMAGE_SCRIPT="board/microchip/mpfs_icicle/post-image.sh"