From 48cc7c655360890d8197493ffacea9c1450cac53 Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Wed, 7 Dec 2022 05:21:33 -0700 Subject: [PATCH] board/zynqmp/kria/patches: fix build by dropping U-Boot patch Since commit 5bbc20154e2291b967b7fc66ca4f85a2b47dcfd1 ("configs/zynqmp_kria_kv260_defconfig: bump to Xilinx 2022.2"), we're using U-Boot version Xilinx 2022.2, which already carries the psu_init_gpl.c, causing the build to fail as our patch doesn't apply. Fix this by dropping the no longer needed patch. Fixes: 5bbc20154e2291b967b7fc66ca4f85a2b47dcfd1 ("configs/zynqmp_kria_kv260_defconfig: bump to Xilinx 2022.2") Signed-off-by: Neal Frager Signed-off-by: Thomas Petazzoni (cherry picked from commit 607665e3cecd967759344d6c702babe82ffa604c) Signed-off-by: Peter Korsgaard --- ...qmp-sm-k26-revA-Fix-DP-PLL-configura.patch | 39 ------------------- configs/zynqmp_kria_kv260_defconfig | 1 - 2 files changed, 40 deletions(-) delete mode 100644 board/zynqmp/kria/patches/uboot/0001-arm64-zynqmp-zynqmp-sm-k26-revA-Fix-DP-PLL-configura.patch diff --git a/board/zynqmp/kria/patches/uboot/0001-arm64-zynqmp-zynqmp-sm-k26-revA-Fix-DP-PLL-configura.patch b/board/zynqmp/kria/patches/uboot/0001-arm64-zynqmp-zynqmp-sm-k26-revA-Fix-DP-PLL-configura.patch deleted file mode 100644 index 99dc056115..0000000000 --- a/board/zynqmp/kria/patches/uboot/0001-arm64-zynqmp-zynqmp-sm-k26-revA-Fix-DP-PLL-configura.patch +++ /dev/null @@ -1,39 +0,0 @@ -From c6677ee92c05e3f0f22cc08e3b309a996292562f Mon Sep 17 00:00:00 2001 -From: Neal Frager -Date: Fri, 13 May 2022 14:02:07 +0100 -Subject: [PATCH 1/1] arm64: zynqmp: zynqmp-sm-k26-revA: Fix DP PLL - configuration - -This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som. - -The Linux DP driver expects the DP to be using the following PLL config: - - DP video PLL should use the VPLL (0x0) - - DP audio PLL should use the RPLL (0x3) - - DP system time clock PLL should use RPLL (0x3) - -Register 0xFD1A0070 configures the DP video PLL. -Register 0xFD1A0074 configures the DP audio PLL. -Register 0xFD1A007C configures the DP system time clock PLL. - -Signed-off-by: Neal Frager ---- - board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c -index ed025790bc..e5598807e8 100644 ---- a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c -+++ b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c -@@ -74,6 +74,9 @@ static unsigned long psu_clock_init_data(void) - psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000A00U); - psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); - psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); -+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); -+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U); -+ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01013803U); - psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); - psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U); --- -2.17.1 - diff --git a/configs/zynqmp_kria_kv260_defconfig b/configs/zynqmp_kria_kv260_defconfig index 7afc7748b0..e5b92fa031 100644 --- a/configs/zynqmp_kria_kv260_defconfig +++ b/configs/zynqmp_kria_kv260_defconfig @@ -37,4 +37,3 @@ BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y BR2_PACKAGE_HOST_DOSFSTOOLS=y BR2_PACKAGE_HOST_GENIMAGE=y BR2_PACKAGE_HOST_MTOOLS=y -BR2_GLOBAL_PATCH_DIR="board/zynqmp/kria/patches"