arch: sparc: Add leon3 cpu type and remove sparc{s,h}fleon{,v8}
There is support for -mcpu=leon3 from gcc 4.8.3. Use this for LEON systems instead of the non-mainline targets sparcsfleon, sparchfleon, sparcsfleonv8, and sparchfleonv8. [Thomas: add Config.in.legacy handling for the removed options.] Signed-off-by: Andreas Larsson <andreas@gaisler.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
This commit is contained in:
Andreas Larsson
Thomas Petazzoni
parent
fd0a51de45
commit
43b78e7285
@ -101,6 +101,38 @@ endif
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###############################################################################
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comment "Legacy options removed in 2014.11"
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config BR2_sparc_sparchfleon
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bool "sparchfleon CPU has been removed"
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select BR2_LEGACY
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help
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The sparchfleon CPU was only supported in a patched gcc 4.4
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version. Its support has been removed in favor of the leon3
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CPU starting from gcc 4.8.x.
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config BR2_sparc_sparchfleonv8
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bool "sparchfleonv8 CPU has been removed"
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select BR2_LEGACY
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help
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The sparchfleonv8 CPU was only supported in a patched gcc
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4.4 version. Its support has been removed in favor of the
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leon3 CPU starting from gcc 4.8.x.
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config BR2_sparc_sparcsfleon
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bool "sparcsfleon CPU has been removed"
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select BR2_LEGACY
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help
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The sparcsfleon CPU was only supported in a patched gcc 4.4
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version. Its support has been removed in favor of the leon3
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CPU starting from gcc 4.8.x.
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config BR2_sparc_sparcsfleonv8
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bool "sparcsfleonv8 CPU has been removed"
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select BR2_LEGACY
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help
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The sparcsfleonv8 CPU was only supported in a patched gcc
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4.4 version. Its support has been removed in favor of the
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leon3 CPU starting from gcc 4.8.x.
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config BR2_PACKAGE_XLIB_LIBPCIACCESS
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bool "xlib-libpciaccess option has been renamed"
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depends on BR2_PACKAGE_XORG7
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@ -7,14 +7,8 @@ choice
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config BR2_sparc_v8
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bool "v8"
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config BR2_sparc_sparchfleon
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bool "hfleon"
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config BR2_sparc_sparchfleonv8
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bool "hfleonv8"
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config BR2_sparc_sparcsfleon
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bool "sfleon"
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config BR2_sparc_sparcsfleonv8
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bool "sfleonv8"
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config BR2_sparc_leon3
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bool "leon3"
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endchoice
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config BR2_ARCH
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@ -30,7 +24,4 @@ config BR2_GCC_TARGET_TUNE
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default "v8" if BR2_sparc_v8
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config BR2_GCC_TARGET_CPU
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default "sparchfleon" if BR2_sparc_sparchfleon
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default "sparchfleonv8" if BR2_sparc_sparchfleonv8
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default "sparcsfleon" if BR2_sparc_sparcsfleon
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default "sparcsfleonv8" if BR2_sparc_sparcsfleonv8
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default "leon3" if BR2_sparc_leon3
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@ -1,239 +0,0 @@
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diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/leon.md gcc-4.4.2/gcc/config/sparc/leon.md
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--- gcc-4.4.2.ori/gcc/config/sparc/leon.md 1970-01-01 01:00:00.000000000 +0100
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+++ gcc-4.4.2/gcc/config/sparc/leon.md 2010-10-19 11:56:58.000000000 +0200
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@@ -0,0 +1,56 @@
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+;; Scheduling description for Leon.
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+;; Copyright (C) 2010 Free Software Foundation, Inc.
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+;;
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+;; This file is part of GCC.
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+;;
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+;; GCC is free software; you can redistribute it and/or modify
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+;; it under the terms of the GNU General Public License as published by
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+;; the Free Software Foundation; either version 3, or (at your option)
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+;; any later version.
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+;;
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+;; GCC is distributed in the hope that it will be useful,
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+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+;; GNU General Public License for more details.
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+;;
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+;; You should have received a copy of the GNU General Public License
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+;; along with GCC; see the file COPYING3. If not see
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+;; <http://www.gnu.org/licenses/>.
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+
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+
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+(define_automaton "leon")
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+
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+(define_cpu_unit "leon_memory, leon_fpalu" "leon")
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+(define_cpu_unit "leon_fpmds" "leon")
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+(define_cpu_unit "write_buf" "leon")
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+
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+(define_insn_reservation "leon_load" 1
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+ (and (eq_attr "cpu" "leon")
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+ (eq_attr "type" "load,sload,fpload"))
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+ "leon_memory")
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+
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+(define_insn_reservation "leon_store" 1
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+ (and (eq_attr "cpu" "leon")
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+ (eq_attr "type" "store,fpstore"))
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+ "leon_memory+write_buf")
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+
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+(define_insn_reservation "leon_fp_alu" 1
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+ (and (eq_attr "cpu" "leon")
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+ (eq_attr "type" "fp,fpmove"))
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+ "leon_fpalu, nothing")
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+
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+(define_insn_reservation "leon_fp_mult" 1
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+ (and (eq_attr "cpu" "leon")
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+ (eq_attr "type" "fpmul"))
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+ "leon_fpmds, nothing")
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+
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+(define_insn_reservation "leon_fp_div" 16
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+ (and (eq_attr "cpu" "leon")
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+ (eq_attr "type" "fpdivs,fpdivd"))
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+ "leon_fpmds, nothing*15")
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+
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+(define_insn_reservation "leon_fp_sqrt" 23
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+ (and (eq_attr "cpu" "leon")
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+ (eq_attr "type" "fpsqrts,fpsqrtd"))
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+ "leon_fpmds, nothing*21")
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+
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diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/sparc.c gcc-4.4.2/gcc/config/sparc/sparc.c
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--- gcc-4.4.2.ori/gcc/config/sparc/sparc.c 2010-10-19 11:55:17.000000000 +0200
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+++ gcc-4.4.2/gcc/config/sparc/sparc.c 2010-10-19 11:56:58.000000000 +0200
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@@ -246,6 +246,30 @@
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0, /* shift penalty */
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};
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+static const
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+struct processor_costs leon_costs = {
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+ COSTS_N_INSNS (1), /* int load */
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+ COSTS_N_INSNS (1), /* int signed load */
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+ COSTS_N_INSNS (1), /* int zeroed load */
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+ COSTS_N_INSNS (1), /* float load */
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+ COSTS_N_INSNS (1), /* fmov, fneg, fabs */
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+ COSTS_N_INSNS (1), /* fadd, fsub */
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+ COSTS_N_INSNS (1), /* fcmp */
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+ COSTS_N_INSNS (1), /* fmov, fmovr */
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+ COSTS_N_INSNS (1), /* fmul */
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+ COSTS_N_INSNS (15), /* fdivs */
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+ COSTS_N_INSNS (15), /* fdivd */
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+ COSTS_N_INSNS (23), /* fsqrts */
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+ COSTS_N_INSNS (23), /* fsqrtd */
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+ COSTS_N_INSNS (5), /* imul */
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+ COSTS_N_INSNS (5), /* imulX */
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+ 0, /* imul bit factor */
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+ COSTS_N_INSNS (5), /* idiv */
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+ COSTS_N_INSNS (5), /* idivX */
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+ COSTS_N_INSNS (1), /* movcc/movr */
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+ 0, /* shift penalty */
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+};
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+
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const struct processor_costs *sparc_costs = &cypress_costs;
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#ifdef HAVE_AS_RELAX_OPTION
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@@ -651,6 +675,10 @@
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{ TARGET_CPU_ultrasparc3, "ultrasparc3" },
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{ TARGET_CPU_niagara, "niagara" },
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{ TARGET_CPU_niagara2, "niagara2" },
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+ { TARGET_CPU_sparchfleon, "sparchfleon" },
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+ { TARGET_CPU_sparchfleonv8, "sparchfleonv8" },
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+ { TARGET_CPU_sparcsfleon, "sparcsfleon" },
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+ { TARGET_CPU_sparcsfleonv8, "sparcsfleonv8" },
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{ 0, 0 }
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};
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const struct cpu_default *def;
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@@ -689,6 +717,11 @@
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/* UltraSPARC T1 */
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{ "niagara", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
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{ "niagara2", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9},
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+ /* SPARC-LEON */
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+ { "sparchfleon", PROCESSOR_LEON, MASK_ISA, MASK_FPU },
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+ { "sparchfleonv8", PROCESSOR_LEON, MASK_ISA & ~(MASK_V8), MASK_V8|MASK_FPU },
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+ { "sparcsfleon", PROCESSOR_LEON, MASK_ISA | MASK_FPU, 0 },
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+ { "sparcsfleonv8", PROCESSOR_LEON, (MASK_ISA | MASK_FPU) & ~(MASK_V8), MASK_V8 },
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{ 0, 0, 0, 0 }
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};
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const struct cpu_table *cpu;
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@@ -855,6 +888,9 @@
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case PROCESSOR_NIAGARA2:
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sparc_costs = &niagara2_costs;
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break;
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+ case PROCESSOR_LEON:
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+ sparc_costs = &leon_costs;
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+ break;
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};
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#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
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diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/sparc.h gcc-4.4.2/gcc/config/sparc/sparc.h
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--- gcc-4.4.2.ori/gcc/config/sparc/sparc.h 2010-10-19 11:55:17.000000000 +0200
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+++ gcc-4.4.2/gcc/config/sparc/sparc.h 2010-10-19 11:56:58.000000000 +0200
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@@ -243,6 +243,10 @@
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#define TARGET_CPU_ultrasparc3 9
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#define TARGET_CPU_niagara 10
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#define TARGET_CPU_niagara2 11
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+#define TARGET_CPU_sparchfleon 12
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+#define TARGET_CPU_sparchfleonv8 13
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+#define TARGET_CPU_sparcsfleon 14
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+#define TARGET_CPU_sparcsfleonv8 15
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#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
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|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
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@@ -299,6 +303,26 @@
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#define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
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#endif
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+#if TARGET_CPU_DEFAULT == TARGET_CPU_sparchfleon
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+#define CPP_CPU32_DEFAULT_SPEC "-Dsparcleon"
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+#define ASM_CPU32_DEFAULT_SPEC ""
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+#endif
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+
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+#if TARGET_CPU_DEFAULT == TARGET_CPU_sparcsfleon
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+#define CPP_CPU32_DEFAULT_SPEC "-Dsparcleon -D_SOFT_FLOAT"
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+#define ASM_CPU32_DEFAULT_SPEC ""
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+#endif
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+
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+#if TARGET_CPU_DEFAULT == TARGET_CPU_sparchfleonv8
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+#define CPP_CPU32_DEFAULT_SPEC "-Dsparcleon -D__sparc_v8__ "
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+#define ASM_CPU32_DEFAULT_SPEC ""
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+#endif
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+
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+#if TARGET_CPU_DEFAULT == TARGET_CPU_sparcsfleonv8
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+#define CPP_CPU32_DEFAULT_SPEC "-Dsparcleon -D__sparc_v8__ -D_SOFT_FLOAT"
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+#define ASM_CPU32_DEFAULT_SPEC ""
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+#endif
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+
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#if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
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#define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
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#define ASM_CPU32_DEFAULT_SPEC ""
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@@ -369,6 +393,10 @@
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%{mcpu=ultrasparc3:-D__sparc_v9__} \
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%{mcpu=niagara:-D__sparc_v9__} \
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%{mcpu=niagara2:-D__sparc_v9__} \
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+%{mcpu=sparchfleon:-Dsparcleon} \
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+%{mcpu=sparchfleonv8:-Dsparcleon -D__sparc_v8__} \
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+%{mcpu=sparcsfleon:-Dsparcleon -D_SOFT_FLOAT} \
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+%{mcpu=sparcsfleonv8:-Dsparcleon -D_SOFT_FLOAT -D__sparc_v8__} \
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%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
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"
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#define CPP_ARCH32_SPEC ""
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@@ -533,6 +561,7 @@
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PROCESSOR_V7,
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PROCESSOR_CYPRESS,
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PROCESSOR_V8,
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+ PROCESSOR_LEON,
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PROCESSOR_SUPERSPARC,
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PROCESSOR_SPARCLITE,
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PROCESSOR_F930,
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diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/sparc.md gcc-4.4.2/gcc/config/sparc/sparc.md
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--- gcc-4.4.2.ori/gcc/config/sparc/sparc.md 2010-10-19 11:55:17.000000000 +0200
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+++ gcc-4.4.2/gcc/config/sparc/sparc.md 2010-10-19 11:56:58.000000000 +0200
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@@ -89,6 +89,7 @@
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"v7,
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cypress,
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v8,
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+ leon,
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supersparc,
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sparclite,f930,f934,
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hypersparc,sparclite86x,
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@@ -320,6 +321,7 @@
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(include "ultra3.md")
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(include "niagara.md")
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(include "niagara2.md")
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+(include "leon.md")
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;; Operand and operator predicates and constraints
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diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/t-leon gcc-4.4.2/gcc/config/sparc/t-leon
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--- gcc-4.4.2.ori/gcc/config/sparc/t-leon 1970-01-01 01:00:00.000000000 +0100
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+++ gcc-4.4.2/gcc/config/sparc/t-leon 2010-10-19 11:56:58.000000000 +0200
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@@ -0,0 +1,16 @@
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+# configuration file for LEON cpu
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+
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+LIB1ASMSRC = sparc/lb1spc.asm
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+LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3
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+
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+# We want fine grained libraries, so use the new code to build the
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+# floating point emulation libraries.
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+FPBIT = fp-bit.c
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+DPBIT = dp-bit.c
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+
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+dp-bit.c: $(srcdir)/config/fp-bit.c
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+ cat $(srcdir)/config/fp-bit.c > dp-bit.c
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+
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+fp-bit.c: $(srcdir)/config/fp-bit.c
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+ echo '#define FLOAT' > fp-bit.c
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+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c
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diff -Naurb gcc-4.4.2.ori/gcc/config.gcc gcc-4.4.2/gcc/config.gcc
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--- gcc-4.4.2.ori/gcc/config.gcc 2010-10-19 11:55:17.000000000 +0200
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+++ gcc-4.4.2/gcc/config.gcc 2010-10-19 11:56:11.000000000 +0200
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@@ -2978,6 +2978,9 @@
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| v9 | ultrasparc | ultrasparc3 | niagara | niagara2)
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# OK
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;;
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+ sparchfleon | sparcsfleon | sparchfleonv8 | sparcsfleonv8 | leon)
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+ tmake_file="${tmake_file} sparc/t-leon"
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+ ;;
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*)
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echo "Unknown cpu used in --with-$which=$val" 1>&2
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exit 1
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@ -8,7 +8,6 @@ config BR2_GCC_SUPPORTS_GRAPHITE
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choice
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prompt "GCC compiler Version"
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default BR2_GCC_VERSION_4_4_X if BR2_sparc_sparchfleon || BR2_sparc_sparchfleonv8 || BR2_sparc_sparcsfleon || BR2_sparc_sparcsfleonv8
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default BR2_GCC_VERSION_4_2_2_AVR32_2_1_5 if BR2_avr32
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default BR2_GCC_VERSION_4_8_ARC if BR2_arc
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default BR2_GCC_VERSION_4_9_X if BR2_microblaze || BR2_powerpc64le
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@ -31,6 +30,8 @@ choice
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depends on !BR2_cortex_a5 && !BR2_cortex_a7 && \
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!BR2_cortex_a12 && !BR2_cortex_a15 && !BR2_fa526 && \
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!BR2_pj4
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# SPARC -mcpu=leon3 appeared in gcc 4.8.3
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depends on !BR2_sparc_leon3
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# ARM EABIhf support appeared in gcc 4.6
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depends on !BR2_ARM_EABIHF
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# ARM VFPv4 support appeared in gcc 4.5
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@ -53,9 +54,8 @@ choice
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!BR2_cortex_a15 && !BR2_fa526 && !BR2_pj4
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# Broken or unsupported PPC cores
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depends on !BR2_power8
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# Broken or unsupported SPARC cores
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depends on !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 \
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&& !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8
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# SPARC -mcpu=leon3 appeared in gcc 4.8.3
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depends on !BR2_sparc_leon3
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# Broken or unsupported X86 cores
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depends on !BR2_x86_corei7 && !BR2_x86_jaguar
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# ARM EABIhf support appeared in gcc 4.6
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@ -73,9 +73,8 @@ choice
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depends on !BR2_cortex_a12 && !BR2_pj4
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# Broken or unsupported PPC cores
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depends on !BR2_power8
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# Broken or unsupported SPARC cores
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depends on !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 \
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&& !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8
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# SPARC -mcpu=leon3 appeared in gcc 4.8.3
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depends on !BR2_sparc_leon3
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# Broken or unsupported x86 cores
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depends on !BR2_x86_jaguar
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select BR2_GCC_NEEDS_MPC
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@ -89,9 +88,6 @@ choice
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depends on !BR2_cortex_a12
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# Broken or unsupported PPC cores
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depends on !BR2_power8
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# Broken or unsupported SPARC cores
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depends on !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 \
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&& !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8
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select BR2_GCC_NEEDS_MPC
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select BR2_GCC_SUPPORTS_GRAPHITE
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|
||||
@ -105,9 +101,6 @@ choice
|
||||
bool "gcc 4.9.x"
|
||||
# Broken or unsupported architectures
|
||||
depends on !BR2_arc && !BR2_avr32 && !BR2_bfin
|
||||
# Broken or unsupported SPARC cores
|
||||
depends on !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 \
|
||||
&& !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8
|
||||
# PR60102 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60102
|
||||
select BR2_GCC_NEEDS_MPC
|
||||
select BR2_GCC_SUPPORTS_GRAPHITE
|
||||
|
||||
Loading…
Reference in New Issue
Block a user