From 23fbc414296c27f5200d21ce5a9ff53f80e5af0c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Sun, 25 Sep 2022 15:22:18 +0200 Subject: [PATCH] configs/aspeed_ast2600evb: set BR2_ARM_FPU_VFPV4D16 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The features of the Cortex A7 CPU on the Aspeed AST2600 A3 SoC are : half thumb fastmult vfp edsp vfpv3 vfpv3d16 tls vfpv4 idiva idivt lpae evtstrm the vfpv3d16 feature bit is common to both vfpv3 and vfpv4. Drop BR2_ARM_FPU_VFPV4 which activates the use of vpfd32 (and breaks user space). Set BR2_ARM_FPU_VFPV4D16 instead. Signed-off-by: Cédric Le Goater Signed-off-by: Thomas Petazzoni (cherry picked from commit 7ccb318d80f0d09e22f944ac9fc618f9abedbe43) Signed-off-by: Peter Korsgaard --- configs/aspeed_ast2600evb_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/aspeed_ast2600evb_defconfig b/configs/aspeed_ast2600evb_defconfig index cd058ad0ac..04239566c8 100644 --- a/configs/aspeed_ast2600evb_defconfig +++ b/configs/aspeed_ast2600evb_defconfig @@ -1,7 +1,7 @@ # Architecture BR2_arm=y BR2_cortex_a7=y -BR2_ARM_FPU_VFPV4=y +BR2_ARM_FPU_VFPV4D16=y # System BR2_TARGET_GENERIC_HOSTNAME="aspeed-evb"