2016-11-07 02:20:02 +01:00
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comment "Linaro toolchains available for Cortex-A + EABIhf"
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depends on BR2_arm
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depends on !BR2_ARM_CPU_ARMV7A || !BR2_ARM_EABIHF
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config BR2_TOOLCHAIN_EXTERNAL_LINARO_ARM
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2018-06-23 11:19:35 +02:00
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bool "Linaro ARM 2018.05"
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2016-11-07 02:20:02 +01:00
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depends on BR2_arm
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2017-09-03 15:17:43 +02:00
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depends on BR2_ARM_CPU_ARMV7A || BR2_ARM_CPU_ARMV8A
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2016-11-07 02:20:02 +01:00
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depends on BR2_HOSTARCH = "x86_64" || BR2_HOSTARCH = "x86"
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depends on BR2_ARM_EABIHF
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2023-08-13 06:47:50 +02:00
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depends on !BR2_ARCH_NEEDS_GCC_AT_LEAST_8
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2016-11-07 02:20:02 +01:00
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select BR2_TOOLCHAIN_EXTERNAL_GLIBC
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select BR2_TOOLCHAIN_HAS_SSP
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select BR2_TOOLCHAIN_HAS_NATIVE_RPC
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select BR2_INSTALL_LIBSTDCPP
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2017-12-21 19:21:17 +01:00
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select BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_10
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select BR2_TOOLCHAIN_GCC_AT_LEAST_7
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2016-11-07 02:20:02 +01:00
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select BR2_TOOLCHAIN_HAS_FORTRAN
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2019-03-26 13:30:46 +01:00
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select BR2_TOOLCHAIN_HAS_OPENMP
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2016-11-07 02:20:02 +01:00
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help
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Linaro toolchain for the ARM architecture. It uses Linaro
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2018-06-23 11:19:35 +02:00
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GCC 2018.05 (based on gcc 7.3.1), Linaro GDB 2018.05 (based on
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GDB 8.1), glibc 2.25, Binutils 2018.05 (based on 2.28). It
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2016-11-07 02:20:02 +01:00
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generates code that runs on all Cortex-A profile devices,
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but tuned for the Cortex-A9. The code generated is Thumb 2,
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with the hard floating point calling convention, and uses
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the VFPv3-D16 FPU instructions.
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