Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
# i386/x86_64 cpu features
|
|
|
|
|
config BR2_X86_CPU_HAS_MMX
|
|
|
|
|
bool
|
2020-05-15 19:53:56 +02:00
|
|
|
config BR2_X86_CPU_HAS_3DNOW
|
|
|
|
|
bool
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_X86_CPU_HAS_SSE
|
|
|
|
|
bool
|
|
|
|
|
config BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
bool
|
|
|
|
|
config BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
bool
|
|
|
|
|
config BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
bool
|
2014-01-02 18:59:45 +01:00
|
|
|
config BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
bool
|
|
|
|
|
config BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
bool
|
2015-03-18 23:01:08 +01:00
|
|
|
config BR2_X86_CPU_HAS_AVX
|
|
|
|
|
bool
|
2015-03-18 23:01:10 +01:00
|
|
|
config BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
bool
|
2022-01-25 00:01:06 +01:00
|
|
|
config BR2_X86_CPU_HAS_AVX512
|
|
|
|
|
bool
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
|
2022-01-25 00:01:14 +01:00
|
|
|
# This list of CPU architecture variant is (loosely) ordered according
|
|
|
|
|
# to the gcc documentation at
|
|
|
|
|
# https://gcc.gnu.org/onlinedocs/gcc-11.2.0/gcc/x86-Options.html
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
choice
|
|
|
|
|
prompt "Target Architecture Variant"
|
|
|
|
|
default BR2_x86_i586 if BR2_i386
|
2018-04-01 07:08:34 +02:00
|
|
|
depends on BR2_i386 || BR2_x86_64
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
help
|
|
|
|
|
Specific CPU variant to use
|
|
|
|
|
|
|
|
|
|
config BR2_x86_i486
|
|
|
|
|
bool "i486"
|
|
|
|
|
depends on !BR2_x86_64
|
|
|
|
|
config BR2_x86_i586
|
|
|
|
|
bool "i586"
|
|
|
|
|
depends on !BR2_x86_64
|
2015-10-19 13:02:52 +02:00
|
|
|
config BR2_x86_x1000
|
|
|
|
|
bool "x1000"
|
|
|
|
|
depends on !BR2_x86_64
|
|
|
|
|
help
|
|
|
|
|
The Intel X1000 is a Pentium class microprocessor in the
|
|
|
|
|
Quark (sub-Atom) Product Line. The X1000 has a bug on the
|
|
|
|
|
lock prefix requiring that prefix must be stripped at build
|
|
|
|
|
time.
|
|
|
|
|
|
2015-10-20 11:32:03 +02:00
|
|
|
See https://en.wikipedia.org/wiki/Intel_Quark
|
|
|
|
|
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_x86_i686
|
|
|
|
|
bool "i686"
|
|
|
|
|
depends on !BR2_x86_64
|
|
|
|
|
config BR2_x86_pentiumpro
|
|
|
|
|
bool "pentium pro"
|
|
|
|
|
depends on !BR2_x86_64
|
|
|
|
|
config BR2_x86_pentium_mmx
|
|
|
|
|
bool "pentium MMX"
|
|
|
|
|
depends on !BR2_x86_64
|
2018-04-01 07:08:34 +02:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_x86_pentium_m
|
|
|
|
|
bool "pentium mobile"
|
2018-04-01 07:08:34 +02:00
|
|
|
depends on !BR2_x86_64
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
config BR2_x86_pentium2
|
|
|
|
|
bool "pentium2"
|
|
|
|
|
depends on !BR2_x86_64
|
2018-04-01 07:08:34 +02:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_x86_pentium3
|
|
|
|
|
bool "pentium3"
|
2018-04-01 07:08:34 +02:00
|
|
|
depends on !BR2_x86_64
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
config BR2_x86_pentium4
|
|
|
|
|
bool "pentium4"
|
2018-04-01 07:08:34 +02:00
|
|
|
depends on !BR2_x86_64
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
config BR2_x86_prescott
|
|
|
|
|
bool "prescott"
|
2018-04-01 07:08:34 +02:00
|
|
|
depends on !BR2_x86_64
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
2022-01-09 09:01:22 +01:00
|
|
|
config BR2_x86_x86_64
|
|
|
|
|
bool "x86-64"
|
|
|
|
|
depends on BR2_x86_64
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
help
|
|
|
|
|
This option corresponds to -march=x86-64, documented as a
|
|
|
|
|
"Generic CPU with 64-bit extensions" by the GCC
|
|
|
|
|
documentation. It is a 64-bit CPU with MMX, SSE and SSE2
|
|
|
|
|
support.
|
2022-01-09 09:01:23 +01:00
|
|
|
config BR2_x86_x86_64_v2
|
|
|
|
|
bool "x86-64-v2"
|
|
|
|
|
depends on BR2_x86_64
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
|
|
|
|
|
help
|
|
|
|
|
This option corresponds to the x86-64-v2 micro-architecture
|
|
|
|
|
level, as defined by the x86-64 psABI document, see
|
|
|
|
|
https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex.
|
|
|
|
|
|
|
|
|
|
It is close to the Nehalem CPU architecture, and is
|
|
|
|
|
applicable for CPUs that support CMPXCHG16B, LAHF-SAHF,
|
|
|
|
|
POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3.
|
|
|
|
|
config BR2_x86_x86_64_v3
|
|
|
|
|
bool "x86-64-v3"
|
|
|
|
|
depends on BR2_x86_64
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
|
|
|
|
|
help
|
|
|
|
|
This option corresponds to the x86-64-v3 micro-architecture
|
|
|
|
|
level, as defined by the x86-64 psABI document, see
|
|
|
|
|
https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex.
|
|
|
|
|
|
|
|
|
|
It is close to the Haswell CPU architecture, and is
|
|
|
|
|
applicable for CPUs that support all of x86-64-v2 plus AVX,
|
|
|
|
|
AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE.
|
|
|
|
|
config BR2_x86_x86_64_v4
|
|
|
|
|
bool "x86-64-v4"
|
|
|
|
|
depends on BR2_x86_64
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
2022-01-25 00:01:07 +01:00
|
|
|
select BR2_X86_CPU_HAS_AVX512
|
2022-01-09 09:01:23 +01:00
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
|
|
|
|
|
help
|
|
|
|
|
This option corresponds to the x86-64-v4 micro-architecture
|
|
|
|
|
level, as defined by the x86-64 psABI document, see
|
|
|
|
|
https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex.
|
|
|
|
|
|
|
|
|
|
It is applicable for CPUs that support all of x86-64-v3 plus
|
|
|
|
|
AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL.
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_x86_nocona
|
|
|
|
|
bool "nocona"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
config BR2_x86_core2
|
|
|
|
|
bool "core2"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
2014-04-27 13:29:15 +02:00
|
|
|
config BR2_x86_corei7
|
|
|
|
|
bool "corei7"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
2022-01-25 00:01:03 +01:00
|
|
|
help
|
|
|
|
|
This option is deprecated. Since gcc 4.9, the gcc option
|
|
|
|
|
"nehalem" is preferred. Use BR2_x86_nehalem instead.
|
|
|
|
|
config BR2_x86_nehalem
|
|
|
|
|
bool "nehalem"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
|
2019-06-11 10:44:09 +02:00
|
|
|
config BR2_x86_westmere
|
|
|
|
|
bool "westmere"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
2022-01-25 00:01:04 +01:00
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
|
2015-03-18 23:01:08 +01:00
|
|
|
config BR2_x86_corei7_avx
|
|
|
|
|
bool "corei7-avx"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
2022-01-25 00:01:03 +01:00
|
|
|
help
|
|
|
|
|
This option is deprecated. Since gcc 4.9, the gcc option
|
|
|
|
|
"sandybridge" is preferred. Use BR2_x86_sandybridge instead.
|
|
|
|
|
config BR2_x86_sandybridge
|
|
|
|
|
bool "sandybridge"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
|
2015-03-18 23:01:10 +01:00
|
|
|
config BR2_x86_core_avx2
|
|
|
|
|
bool "core-avx2"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
2022-01-25 00:01:03 +01:00
|
|
|
help
|
|
|
|
|
This option is deprecated. Since gcc 4.9, the gcc option
|
|
|
|
|
"haswell" is preferred. Use BR2_x86_haswell instead.
|
|
|
|
|
config BR2_x86_haswell
|
|
|
|
|
bool "haswell"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
|
2022-01-25 00:01:05 +01:00
|
|
|
config BR2_x86_broadwell
|
|
|
|
|
bool "broadwell"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
|
2022-01-25 00:01:06 +01:00
|
|
|
config BR2_x86_skylake
|
|
|
|
|
bool "skylake"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_x86_atom
|
|
|
|
|
bool "atom"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
2022-01-25 00:01:03 +01:00
|
|
|
help
|
|
|
|
|
This option is deprecated. Since gcc 4.9, the gcc option
|
2022-05-15 19:19:54 +02:00
|
|
|
"bonnell" is preferred. Use BR2_x86_bonnell instead.
|
|
|
|
|
config BR2_x86_bonnell
|
|
|
|
|
bool "bonnell"
|
2022-01-25 00:01:03 +01:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
|
2017-10-24 14:22:06 +02:00
|
|
|
config BR2_x86_silvermont
|
|
|
|
|
bool "silvermont"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
2022-01-25 00:01:04 +01:00
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
|
2022-01-25 00:01:11 +01:00
|
|
|
config BR2_x86_goldmont
|
|
|
|
|
bool "goldmont"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
|
|
|
|
|
config BR2_x86_goldmont_plus
|
|
|
|
|
bool "goldmont-plus"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
|
|
|
|
|
config BR2_x86_tremont
|
|
|
|
|
bool "tremont"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
|
2022-01-25 00:01:06 +01:00
|
|
|
config BR2_x86_skylake_avx512
|
|
|
|
|
bool "skylake-avx512"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX512
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
|
2022-01-25 00:01:10 +01:00
|
|
|
config BR2_x86_cannonlake
|
|
|
|
|
bool "cannonlake"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX512
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
|
|
|
|
|
config BR2_x86_icelake_client
|
|
|
|
|
bool "icelake-client"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX512
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
|
|
|
|
|
config BR2_x86_icelake_server
|
|
|
|
|
bool "icelake-server"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX512
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
|
2022-01-25 00:01:11 +01:00
|
|
|
config BR2_x86_cascadelake
|
|
|
|
|
bool "cascadelake"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX512
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
|
2022-01-25 00:01:12 +01:00
|
|
|
config BR2_x86_cooperlake
|
|
|
|
|
bool "cooperlake"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX512
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_10
|
2022-01-25 00:01:11 +01:00
|
|
|
config BR2_x86_tigerlake
|
|
|
|
|
bool "tigerlake"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX512
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
|
2022-01-25 00:01:13 +01:00
|
|
|
config BR2_x86_sapphirerapids
|
|
|
|
|
bool "sapphirerapids"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX512
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
|
|
|
|
|
config BR2_x86_alderlake
|
|
|
|
|
bool "alderlake"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
|
|
|
|
|
config BR2_x86_rocketlake
|
|
|
|
|
bool "rocketlake"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX2
|
|
|
|
|
select BR2_X86_CPU_HAS_AVX512
|
|
|
|
|
select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_x86_k6
|
|
|
|
|
bool "k6"
|
|
|
|
|
depends on !BR2_x86_64
|
2018-04-01 07:08:34 +02:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_x86_k6_2
|
|
|
|
|
bool "k6-2"
|
|
|
|
|
depends on !BR2_x86_64
|
2018-04-01 07:08:34 +02:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
2020-05-15 19:53:56 +02:00
|
|
|
select BR2_X86_CPU_HAS_3DNOW
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_x86_athlon
|
|
|
|
|
bool "athlon"
|
|
|
|
|
depends on !BR2_x86_64
|
2018-04-01 07:08:34 +02:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
2020-05-15 19:53:56 +02:00
|
|
|
select BR2_X86_CPU_HAS_3DNOW
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_x86_athlon_4
|
|
|
|
|
bool "athlon-4"
|
2018-04-01 07:08:34 +02:00
|
|
|
depends on !BR2_x86_64
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
2020-05-15 19:53:56 +02:00
|
|
|
select BR2_X86_CPU_HAS_3DNOW
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_x86_opteron
|
|
|
|
|
bool "opteron"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
config BR2_x86_opteron_sse3
|
|
|
|
|
bool "opteron w/ SSE3"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
config BR2_x86_barcelona
|
|
|
|
|
bool "barcelona"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
2014-01-15 23:17:10 +01:00
|
|
|
config BR2_x86_jaguar
|
|
|
|
|
bool "jaguar"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
2014-01-20 18:35:17 +01:00
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
2015-03-03 16:52:30 +01:00
|
|
|
config BR2_x86_steamroller
|
|
|
|
|
bool "steamroller"
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE2
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSSE3
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE4
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE42
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_x86_geode
|
2023-07-23 13:20:22 +02:00
|
|
|
bool "geode (no mmx)"
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
depends on !BR2_x86_64
|
2023-07-23 13:20:22 +02:00
|
|
|
help
|
|
|
|
|
For several variant of geode which have not MMX support.
|
|
|
|
|
See https://en.wikipedia.org/wiki/Geode_%28processor%29 to
|
|
|
|
|
determine if your particular Geode processor supports MMX or
|
|
|
|
|
not.
|
|
|
|
|
config BR2_x86_geode_mmx
|
|
|
|
|
bool "geode (with mmx)"
|
|
|
|
|
depends on !BR2_x86_64
|
|
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
help
|
|
|
|
|
For several variant of geode which have MMX support.
|
|
|
|
|
See https://en.wikipedia.org/wiki/Geode_%28processor%29 to
|
|
|
|
|
determine if your particular Geode processor supports MMX or
|
|
|
|
|
not.
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_x86_c3
|
|
|
|
|
bool "Via/Cyrix C3 (Samuel/Ezra cores)"
|
|
|
|
|
depends on !BR2_x86_64
|
2018-04-01 07:08:34 +02:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
2020-05-15 19:53:56 +02:00
|
|
|
select BR2_X86_CPU_HAS_3DNOW
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_x86_c32
|
|
|
|
|
bool "Via C3-2 (Nehemiah cores)"
|
2018-04-01 07:08:34 +02:00
|
|
|
depends on !BR2_x86_64
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
|
|
|
|
select BR2_X86_CPU_HAS_SSE
|
|
|
|
|
config BR2_x86_winchip_c6
|
|
|
|
|
bool "IDT Winchip C6"
|
|
|
|
|
depends on !BR2_x86_64
|
2018-04-01 07:08:34 +02:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
config BR2_x86_winchip2
|
|
|
|
|
bool "IDT Winchip 2"
|
|
|
|
|
depends on !BR2_x86_64
|
2018-04-01 07:08:34 +02:00
|
|
|
select BR2_X86_CPU_HAS_MMX
|
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-03 09:27:59 +01:00
|
|
|
endchoice
|
arch: improve definition of gcc mtune, mcpu, etc.
As suggested by Yann E. Morin, there is a better way than our current
big Config.in.common to define the gcc mtune, mcpu, march,
etc. values. We can split the setting of those values in each
architecture file, which makes a lot more sense.
Therefore, the Config.in file now creates empty kconfig variables
BR2_ARCH, BR2_ENDIAN, BR2_GCC_TARGET_TUNE, BR2_GCC_TARGET_ARCH,
BR2_GCC_TARGET_ABI and BR2_GCC_TARGET_CPU. The values of those
variables are set by the individual Config.in.<arch> files. This is
possible because such files are now only conditionally included
depending on the top-level architecture that has been selected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-15 04:53:48 +01:00
|
|
|
|
|
|
|
|
config BR2_ARCH
|
|
|
|
|
default "i486" if BR2_x86_i486
|
|
|
|
|
default "i586" if BR2_x86_i586
|
2015-10-19 13:02:52 +02:00
|
|
|
default "i586" if BR2_x86_x1000
|
arch: improve definition of gcc mtune, mcpu, etc.
As suggested by Yann E. Morin, there is a better way than our current
big Config.in.common to define the gcc mtune, mcpu, march,
etc. values. We can split the setting of those values in each
architecture file, which makes a lot more sense.
Therefore, the Config.in file now creates empty kconfig variables
BR2_ARCH, BR2_ENDIAN, BR2_GCC_TARGET_TUNE, BR2_GCC_TARGET_ARCH,
BR2_GCC_TARGET_ABI and BR2_GCC_TARGET_CPU. The values of those
variables are set by the individual Config.in.<arch> files. This is
possible because such files are now only conditionally included
depending on the top-level architecture that has been selected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-15 04:53:48 +01:00
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default "i586" if BR2_x86_pentium_mmx
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default "i586" if BR2_x86_geode
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default "i586" if BR2_x86_c3
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default "i686" if BR2_x86_c32
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default "i586" if BR2_x86_winchip_c6
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default "i586" if BR2_x86_winchip2
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2022-01-25 00:01:02 +01:00
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# We use the property of Kconfig that the first match of a
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# list of default will be chosen. So the following entry will
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# not match for all BR2_i386=y configurations, but only the
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# ones that didn't match any of the previous cases (i486,
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# i586).
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default "i686" if BR2_i386
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arch: improve definition of gcc mtune, mcpu, etc.
As suggested by Yann E. Morin, there is a better way than our current
big Config.in.common to define the gcc mtune, mcpu, march,
etc. values. We can split the setting of those values in each
architecture file, which makes a lot more sense.
Therefore, the Config.in file now creates empty kconfig variables
BR2_ARCH, BR2_ENDIAN, BR2_GCC_TARGET_TUNE, BR2_GCC_TARGET_ARCH,
BR2_GCC_TARGET_ABI and BR2_GCC_TARGET_CPU. The values of those
variables are set by the individual Config.in.<arch> files. This is
possible because such files are now only conditionally included
depending on the top-level architecture that has been selected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-15 04:53:48 +01:00
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default "x86_64" if BR2_x86_64
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core: introduce NORMALIZED_ARCH as non-kernel replacement for KERNEL_ARCH
The variable 'KERNEL_ARCH' is actually a normalized version of
'ARCH'/'BR2_ARCH'. For example, 'arcle' and 'arceb' both become 'arc', just
as all powerpc variants become 'powerpc'.
It is presumably called 'KERNEL_ARCH' because the Linux kernel is typically
the first place where support for a new architecture is added, and thus is
the entity that defines the normalized name.
However, the term 'KERNEL_ARCH' can also be interpreted as 'the architecture
used by the kernel', which need not be exactly the same as 'the normalized
name for a certain arch'. In particular, for cases where a 64-bit
architecture is running a 64-bit kernel but 32-bit userspace. Examples
include:
* aarch64 architecture, with aarch64 kernel and 32-bit (ARM) userspace
* x86_64 architecture, with x86_64 kernel and 32-bit (i386) userspace
In such cases, the 'architecture used by the kernel' needs to refer to the
64-bit name (aarch64, x86_64), whereas all userspace applications need to
refer the, potentially normalized, 32-bit name.
This means that there need to be two different variables:
KERNEL_ARCH: the architecture used by the kernel
NORMALIZED_ARCH: the normalized name for the current userspace architecture
At this moment, both will actually have the same content. But a subsequent
patch will add basic support for situations described above, in which
KERNEL_ARCH may become overwritten to the 64-bit architecture, while
NORMALIZED_ARCH needs to remain the same (32-bit) case.
This commit replaces use of KERNEL_ARCH where actually the userspace arch is
needed. Places that use KERNEL_ARCH in combination with building of kernel
modules are not touched.
There may be cases where a package builds both a kernel module as userspace,
in which case it may need to know about both KERNEL_ARCH and
NORMALIZED_ARCH, for the case where they differ. But this is to be fixed on
a per-need basis.
Signed-off-by: Thomas De Schampheleire <thomas.de_schampheleire@nokia.com>
Reviewed-by: Romain Naour <romain.naour@gmail.com>
[Arnout: Also rename BR2_KERNEL_ARCH to BR2_NORMALIZED_ARCH]
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
2022-01-15 21:03:00 +01:00
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|
|
config BR2_NORMALIZED_ARCH
|
2022-01-15 21:02:59 +01:00
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|
|
default "i386" if !BR2_x86_64
|
|
|
|
|
default "x86_64" if BR2_x86_64
|
|
|
|
|
|
arch: improve definition of gcc mtune, mcpu, etc.
As suggested by Yann E. Morin, there is a better way than our current
big Config.in.common to define the gcc mtune, mcpu, march,
etc. values. We can split the setting of those values in each
architecture file, which makes a lot more sense.
Therefore, the Config.in file now creates empty kconfig variables
BR2_ARCH, BR2_ENDIAN, BR2_GCC_TARGET_TUNE, BR2_GCC_TARGET_ARCH,
BR2_GCC_TARGET_ABI and BR2_GCC_TARGET_CPU. The values of those
variables are set by the individual Config.in.<arch> files. This is
possible because such files are now only conditionally included
depending on the top-level architecture that has been selected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-11-15 04:53:48 +01:00
|
|
|
config BR2_ENDIAN
|
|
|
|
|
default "LITTLE"
|
|
|
|
|
|
|
|
|
|
config BR2_GCC_TARGET_ARCH
|
2012-11-15 04:53:53 +01:00
|
|
|
default "i486" if BR2_x86_i486
|
|
|
|
|
default "i586" if BR2_x86_i586
|
2015-10-19 13:02:52 +02:00
|
|
|
default "i586" if BR2_x86_x1000
|
2012-11-15 04:53:53 +01:00
|
|
|
default "pentium-mmx" if BR2_x86_pentium_mmx
|
|
|
|
|
default "i686" if BR2_x86_i686
|
|
|
|
|
default "pentiumpro" if BR2_x86_pentiumpro
|
|
|
|
|
default "pentium-m" if BR2_x86_pentium_m
|
|
|
|
|
default "pentium2" if BR2_x86_pentium2
|
|
|
|
|
default "pentium3" if BR2_x86_pentium3
|
|
|
|
|
default "pentium4" if BR2_x86_pentium4
|
|
|
|
|
default "prescott" if BR2_x86_prescott
|
2022-01-09 09:01:22 +01:00
|
|
|
default "x86-64" if BR2_x86_x86_64
|
2022-01-09 09:01:23 +01:00
|
|
|
default "x86-64-v2" if BR2_x86_x86_64_v2
|
|
|
|
|
default "x86-64-v3" if BR2_x86_x86_64_v3
|
|
|
|
|
default "x86-64-v4" if BR2_x86_x86_64_v4
|
2012-11-15 04:53:53 +01:00
|
|
|
default "nocona" if BR2_x86_nocona
|
|
|
|
|
default "core2" if BR2_x86_core2
|
2014-04-27 13:29:15 +02:00
|
|
|
default "corei7" if BR2_x86_corei7
|
2022-01-25 00:01:03 +01:00
|
|
|
default "nehalem" if BR2_x86_nehalem
|
2015-03-18 23:01:08 +01:00
|
|
|
default "corei7-avx" if BR2_x86_corei7_avx
|
2022-01-25 00:01:03 +01:00
|
|
|
default "sandybridge" if BR2_x86_sandybridge
|
2015-03-18 23:01:10 +01:00
|
|
|
default "core-avx2" if BR2_x86_core_avx2
|
2022-01-25 00:01:03 +01:00
|
|
|
default "haswell" if BR2_x86_haswell
|
2022-01-25 00:01:05 +01:00
|
|
|
default "broadwell" if BR2_x86_broadwell
|
2022-01-25 00:01:06 +01:00
|
|
|
default "skylake" if BR2_x86_skylake
|
2012-11-15 04:53:53 +01:00
|
|
|
default "atom" if BR2_x86_atom
|
2022-05-15 19:19:54 +02:00
|
|
|
default "bonnell" if BR2_x86_bonnell
|
2019-06-11 10:44:09 +02:00
|
|
|
default "westmere" if BR2_x86_westmere
|
2017-10-24 14:22:06 +02:00
|
|
|
default "silvermont" if BR2_x86_silvermont
|
2022-01-25 00:01:11 +01:00
|
|
|
default "goldmont" if BR2_x86_goldmont
|
|
|
|
|
default "goldmont-plus" if BR2_x86_goldmont_plus
|
|
|
|
|
default "tremont" if BR2_x86_tremont
|
2022-01-25 00:01:06 +01:00
|
|
|
default "skylake-avx512" if BR2_x86_skylake_avx512
|
2022-01-25 00:01:10 +01:00
|
|
|
default "cannonlake" if BR2_x86_cannonlake
|
|
|
|
|
default "icelake-client" if BR2_x86_icelake_client
|
|
|
|
|
default "icelake-server" if BR2_x86_icelake_server
|
2022-01-25 00:01:11 +01:00
|
|
|
default "cascadelake" if BR2_x86_cascadelake
|
2022-01-25 00:01:12 +01:00
|
|
|
default "cooperlake" if BR2_x86_cooperlake
|
2022-01-25 00:01:11 +01:00
|
|
|
default "tigerlake" if BR2_x86_tigerlake
|
2022-01-25 00:01:13 +01:00
|
|
|
default "sapphirerapids" if BR2_x86_sapphirerapids
|
|
|
|
|
default "alderlake" if BR2_x86_alderlake
|
|
|
|
|
default "rocketlake" if BR2_x86_rocketlake
|
2012-11-15 04:53:53 +01:00
|
|
|
default "k8" if BR2_x86_opteron
|
|
|
|
|
default "k8-sse3" if BR2_x86_opteron_sse3
|
|
|
|
|
default "barcelona" if BR2_x86_barcelona
|
2014-01-15 23:17:10 +01:00
|
|
|
default "btver2" if BR2_x86_jaguar
|
2015-03-03 16:52:30 +01:00
|
|
|
default "bdver3" if BR2_x86_steamroller
|
2012-11-15 04:53:53 +01:00
|
|
|
default "k6" if BR2_x86_k6
|
|
|
|
|
default "k6-2" if BR2_x86_k6_2
|
|
|
|
|
default "athlon" if BR2_x86_athlon
|
|
|
|
|
default "athlon-4" if BR2_x86_athlon_4
|
|
|
|
|
default "winchip-c6" if BR2_x86_winchip_c6
|
|
|
|
|
default "winchip2" if BR2_x86_winchip2
|
|
|
|
|
default "c3" if BR2_x86_c3
|
|
|
|
|
default "c3-2" if BR2_x86_c32
|
|
|
|
|
default "geode" if BR2_x86_geode
|
2017-03-19 14:07:51 +01:00
|
|
|
|
|
|
|
|
config BR2_READELF_ARCH_NAME
|
|
|
|
|
default "Intel 80386" if BR2_i386
|
|
|
|
|
default "Advanced Micro Devices X86-64" if BR2_x86_64
|
2019-05-03 15:10:17 +02:00
|
|
|
|
|
|
|
|
# vim: ft=kconfig
|
|
|
|
|
# -*- mode:kconfig; -*-
|
