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kumquat-buildroot/board/andes/ae350/ae350.dts

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board/andes/ae350: add support for Andes AE350 This patch provides defconfig and basic support for Andes 45 series RISC-V architecture on AE350 platform. http://www.andestech.com/en/products-solutions/andeshape-platforms/ae350-axi-based-platform-pre-integrated-with-n25f-nx25f-a25-ax25/ Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Signed-off-by: Alan Kao <alankao@andestech.com> Reviewed-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Tested-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
2022-02-25 10:25:08 +01:00
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "andestech,ae350";
model = "andestech,ax45";
aliases {
uart0 = &serial0;
spi0 = &spi;
};
chosen {
bootargs = "console=ttyS0,38400n8 earlycon=sbi debug loglevel=7";
stdout-path = "uart0:38400n8";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <60000000>;
CPU0: cpu@0 {
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-1p1xdsp0p0";
riscv,priv-major = <1>;
riscv,priv-minor = <10>;
mmu-type = "riscv,sv48";
clock-frequency = <60000000>;
i-cache-size = <0x8000>;
i-cache-sets = <256>;
i-cache-block-size = <64>;
i-cache-line-size = <64>;
d-cache-size = <0x8000>;
d-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-line-size = <64>;
next-level-cache = <&L2>;
CPU0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
CPU1: cpu@1 {
device_type = "cpu";
reg = <1>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-1p1xdsp0p0";
riscv,priv-major = <1>;
riscv,priv-minor = <10>;
mmu-type = "riscv,sv48";
clock-frequency = <60000000>;
i-cache-size = <0x8000>;
i-cache-sets = <256>;
i-cache-block-size = <64>;
i-cache-line-size = <64>;
d-cache-size = <0x8000>;
d-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-line-size = <64>;
next-level-cache = <&L2>;
CPU1_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
CPU2: cpu@2 {
device_type = "cpu";
reg = <2>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-1p1xdsp0p0";
riscv,priv-major = <1>;
riscv,priv-minor = <10>;
mmu-type = "riscv,sv48";
clock-frequency = <60000000>;
i-cache-size = <0x8000>;
i-cache-sets = <256>;
i-cache-block-size = <64>;
i-cache-line-size = <64>;
d-cache-size = <0x8000>;
d-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-line-size = <64>;
next-level-cache = <&L2>;
CPU2_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
CPU3: cpu@3 {
device_type = "cpu";
reg = <3>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-1p1xdsp0p0";
riscv,priv-major = <1>;
riscv,priv-minor = <10>;
mmu-type = "riscv,sv48";
clock-frequency = <60000000>;
i-cache-size = <0x8000>;
i-cache-sets = <256>;
i-cache-block-size = <64>;
i-cache-line-size = <64>;
d-cache-size = <0x8000>;
d-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-line-size = <64>;
next-level-cache = <&L2>;
CPU3_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
};
L2: l2-cache@e0500000 {
compatible = "cache";
cache-level = <2>;
cache-size = <0x80000>;
reg = <0x00000000 0xe0500000 0x00000000 0x00001000>;
andes,inst-prefetch = <3>;
andes,data-prefetch = <3>;
// The value format is <XRAMOCTL XRAMICTL>
andes,tag-ram-ctl = <0 0>;
andes,data-ram-ctl = <0 0>;
};
memory@0 {
reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
device_type = "memory";
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "andestech,riscv-ae350-soc", "simple-bus";
ranges;
plic0: interrupt-controller@e4000000 {
compatible = "riscv,plic0";
reg = <0x00000000 0xe4000000 0x00000000 0x02000000>;
interrupts-extended = < &CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9 &CPU2_intc 11 &CPU2_intc 9 &CPU3_intc 11 &CPU3_intc 9>;
interrupt-controller;
#address-cells = <2>;
#interrupt-cells = <2>;
riscv,ndev = <71>;
};
plic1: interrupt-controller@e6400000 {
compatible = "riscv,plic1";
reg = <0x00000000 0xe6400000 0x00000000 0x00400000>;
interrupts-extended = < &CPU0_intc 3 &CPU1_intc 3 &CPU2_intc 3 &CPU3_intc 3>;
interrupt-controller;
#address-cells = <2>;
#interrupt-cells = <2>;
riscv,ndev = <4>;
};
plmt0: plmt0@e6000000 {
compatible = "riscv,plmt0";
reg = <0x00000000 0xe6000000 0x00000000 0x00100000>;
interrupts-extended = < &CPU0_intc 7 &CPU1_intc 7 &CPU2_intc 7 &CPU3_intc 7>;
};
spiclk: virt_100mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
timer0: timer@f0400000 {
compatible = "andestech,atcpit100";
reg = <0x00000000 0xf0400000 0x00000000 0x00001000>;
interrupts = <3 4>;
interrupt-parent = <&plic0>;
clock-frequency = <60000000>;
};
pwm: pwm@f0400000 {
compatible = "andestech,atcpit100-pwm";
reg = <0x00000000 0xf0400000 0x00000000 0x00001000>;
interrupts = <3 4>;
interrupt-parent = <&plic0>;
clock-frequency = <60000000>;
pwm-cells = <2>;
};
wdt: wdt@f0500000 {
compatible = "andestech,atcwdt200";
reg = <0x00000000 0xf0500000 0x00000000 0x00001000>;
interrupts = <3 4>;
interrupt-parent = <&plic0>;
clock-frequency = <15000000>;
};
serial0: serial@f0300000 {
compatible = "andestech,uart16550", "ns16550a";
reg = <0x00000000 0xf0300000 0x00000000 0x00001000>;
interrupts = <9 4>;
interrupt-parent = <&plic0>;
clock-frequency = <19660800>;
reg-shift = <2>;
reg-offset = <32>;
no-loopback-test = <1>;
};
rtc0: rtc@f0600000 {
compatible = "andestech,atcrtc100";
reg = <0x00000000 0xf0600000 0x00000000 0x00001000>;
interrupts = <1 4 2 4>;
interrupt-parent = <&plic0>;
wakeup-source;
};
gpio: gpio@f0700000 {
compatible = "andestech,atcgpio100";
reg = <0x00000000 0xf0700000 0x00000000 0x00001000>;
interrupts = <7 4>;
interrupt-parent = <&plic0>;
wakeup-source;
};
mac0: mac@e0100000 {
compatible = "andestech,atmac100";
reg = <0x00000000 0xe0100000 0x00000000 0x00001000>;
interrupts = <19 4>;
interrupt-parent = <&plic0>;
dma-coherent;
};
smu: smu@f0100000 {
compatible = "andestech,atcsmu";
reg = <0x00000000 0xf0100000 0x00000000 0x00001000>;
};
mmc0: mmc@f0e00000 {
compatible = "andestech,atfsdc010";
reg = <0x00000000 0xf0e00000 0x00000000 0x00001000>;
interrupts = <18 4>;
interrupt-parent = <&plic0>;
clock-freq-min-max = <400000 100000000>;
max-frequency = <100000000>;
fifo-depth = <16>;
cap-sd-highspeed;
dma-coherent;
};
dma0: dma@f0c00000 {
compatible = "andestech,atcdmac300";
reg = <0x00000000 0xf0c00000 0x00000000 0x00001000>;
interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
interrupt-parent = <&plic0>;
dma-channels = <8>;
};
lcd0: lcd@e0200000 {
compatible = "andestech,atflcdc100";
reg = <0x00000000 0xe0200000 0x00000000 0x00001000>;
interrupts = <20 4>;
interrupt-parent = <&plic0>;
dma-coherent;
};
pmu: pmu {
compatible = "riscv,andes-pmu";
device_type = "pmu";
};
spi: spi@f0b00000 {
compatible = "andestech,atcspi200";
reg = <0x00000000 0xf0b00000 0x00000000 0x00001000>;
interrupts = <4 4>;
interrupt-parent = <&plic0>;
#address-cells = <1>;
#size-cells = <0>;
num-cs = <1>;
clocks = <&spiclk>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x00000000>;
spi-max-frequency = <50000000>;
spi-cpol;
spi-cpha;
};
};
};
};
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