41 lines
1.7 KiB
Diff
41 lines
1.7 KiB
Diff
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From aaaa10b613165b7790fe1c084de007240b5bd77a Mon Sep 17 00:00:00 2001
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From: Neal Frager <neal.frager@amd.com>
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Date: Thu, 5 May 2022 13:34:43 +0100
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Subject: [PATCH 1/1] arm64: zynqmp: zynqmp-zcu102-revA: Fix DP PLL
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configuration
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This patch fixes the DP audio and video PLL configurations
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for the zynqmp-zcu106-revA evaluation board
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The Linux DP driver expects the DP to be using the following PLL config:
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- DP video PLL should use the VPLL (0x0)
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- DP audio PLL should use the RPLL (0x3)
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Register 0xFD1A0070 configures the DP video PLL.
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Register 0xFD1A0074 configures the DP audio PLL.
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Signed-off-by: Neal Frager <neal.frager@amd.com>
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Signed-off-by: Michal Simek <michal.simek@amd.com>
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---
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board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
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index 15f0be1a43..cbc436289f 100644
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--- a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
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+++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
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@@ -81,8 +81,8 @@ static unsigned long psu_clock_init_data(void)
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psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
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psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
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psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
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- psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U);
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- psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U);
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+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
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+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
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psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U);
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psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
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psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
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--
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2.17.1
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