2012-11-15 04:53:52 +01:00
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choice
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prompt "Target Architecture Variant"
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depends on BR2_xtensa
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default BR2_xtensa_fsf
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2012-11-20 09:31:36 +01:00
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config BR2_XTENSA_CUSTOM
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2015-06-04 00:34:03 +02:00
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select BR2_ARCH_HAS_MMU_OPTIONAL
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2012-11-15 04:53:52 +01:00
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bool "Custom Xtensa processor configuration"
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config BR2_xtensa_fsf
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2015-06-04 00:34:03 +02:00
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select BR2_ARCH_HAS_MMU_MANDATORY
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2012-11-15 04:53:52 +01:00
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bool "fsf - Default configuration"
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endchoice
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2012-11-20 09:31:36 +01:00
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config BR2_XTENSA_CUSTOM_NAME
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string "Custom Xtensa processor configuration name"
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depends on BR2_XTENSA_CUSTOM
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2012-11-15 04:53:52 +01:00
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default ""
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help
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Name given to a custom Xtensa processor configuration.
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2012-11-20 09:31:36 +01:00
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config BR2_XTENSA_CORE_NAME
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2012-11-15 04:53:52 +01:00
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string
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2012-11-20 09:31:36 +01:00
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default BR2_XTENSA_CUSTOM_NAME if BR2_XTENSA_CUSTOM
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2012-11-15 04:53:52 +01:00
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default "" if BR2_xtensa_fsf
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2012-11-20 09:31:36 +01:00
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config BR2_XTENSA_OVERLAY_DIR
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2012-11-15 04:53:52 +01:00
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string "Overlay directory for custom configuration"
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2012-11-20 09:31:36 +01:00
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depends on BR2_XTENSA_CUSTOM
|
2012-11-15 04:53:52 +01:00
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default ""
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help
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2012-11-20 09:31:36 +01:00
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Provide the directory path that contains the overlay file
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for a custom processor configuration. The path is relative
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to the top directory of buildroot.
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These overlay files are tar packages with updated configuration
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files for various toolchain packages and Xtensa processor
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configurations. They are provided by the processor vendor or
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directly from Tensilica.
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2012-11-15 04:53:52 +01:00
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|
2015-05-05 18:18:24 +02:00
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choice
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prompt "Target Architecture Endianness"
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depends on BR2_XTENSA_CUSTOM
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default BR2_XTENSA_LITTLE_ENDIAN
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config BR2_XTENSA_LITTLE_ENDIAN
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bool "Little endian"
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config BR2_XTENSA_BIG_ENDIAN
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bool "Big endian"
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endchoice
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config BR2_ENDIAN
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default "LITTLE" if BR2_XTENSA_LITTLE_ENDIAN
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default "BIG" if BR2_xtensa_fsf || BR2_XTENSA_BIG_ENDIAN
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|
2012-11-15 04:53:51 +01:00
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config BR2_ARCH
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default "xtensa" if BR2_xtensa
|
2017-03-19 14:07:51 +01:00
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config BR2_READELF_ARCH_NAME
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default "Tensilica Xtensa Processor"
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